A semiconductor device capable of performing product-sum operation with high layout flexibility is provided. In the semiconductor device, a first layer, a second layer, and a third layer are formed in this order. The first layer includes a first cell, a first circuit, a first wiring, and a second wiring adjacent to the first wiring. The second layer includes a third wiring and a fourth wiring adjacent to the third wiring. The third layer includes an electrode and a sensor. The first circuit includes a switch. The sensor is electrically connected to the third wiring through the electrode and a first plug, a first terminal of the switch is electrically connected to the third wiring through a second plug, and a second terminal of the switch is electrically connected to the first cell through the first wiring. The electrode includes a region overlapping with the sensor and a region overlapping with the first plug. Note that the first to fourth wirings are parallel to each other, and the distance between the third wiring and the fourth wiring is greater than or equal to 0.9 times and less than or equal to 1.1 times the distance between the first wiring and the second wiring.

A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. The analog crossbar array can be implemented in CMOS and memristors or a hybrid solution including a combination of CMOS and memristors.

An intensity spectrum designing unit of a data generating device includes an initial value setting unit that sets a plurality of objects of a first generation of an intensity spectrum function A(?) and a phase spectrum function ?(?), an evaluation value calculating unit that calculates an evaluation value for each of a plurality of objects of an n-th generation, an object selecting unit that selects two or more objects used for generating a plurality of objects of an (n+1)-th generation among objects of the n-th generation on the basis of superiority of the evaluation value, and a next-generation generating unit that generates a plurality of objects of the (n+1)-th generation on the basis of the selected two or more objects. The evaluation value calculating unit, the object selecting unit, and the next-generation generating unit repeat processes while 1 is added to n until a predetermined condition is satisfied.

An intensity spectrum designing unit of a data generating device includes an initial value setting unit that sets a plurality of objects of a first generation of an intensity spectrum function A(?) and a phase spectrum function ?(?), an evaluation value calculating unit that calculates an evaluation value for each of a plurality of objects of an n-th generation, an object selecting unit that selects two or more objects used for generating a plurality of objects of an (n+1)-th generation among objects of the n-th generation on the basis of superiority of the evaluation value, and a next-generation generating unit that generates a plurality of objects of the (n+1)-th generation on the basis of the selected two or more objects. The evaluation value calculating unit, the object selecting unit, and the next-generation generating unit repeat processes while 1 is added to n until a predetermined condition is satisfied.

An intensity spectrum designing unit of a data generating device includes an initial value setting unit that sets a plurality of objects of a first generation of an intensity spectrum function A(?) and a phase spectrum function ?(?), an evaluation value calculating unit that calculates an evaluation value for each of a plurality of objects of an n-th generation, an object selecting unit that selects two or more objects used for generating a plurality of objects of an (n+1)-th generation among objects of the n-th generation on the basis of superiority of the evaluation value, and a next-generation generating unit that generates a plurality of objects of the (n+1)-th generation on the basis of the selected two or more objects. The evaluation value calculating unit, the object selecting unit, and the next-generation generating unit repeat processes while 1 is added to n until a predetermined condition is satisfied.

It is provided a signal processing system, comprising at least a first, a second and a third digital-to-analog converter (DAC); a processing unit configured for splitting a sampled signal into a first and a second signal corresponding to different frequency portions of the sampled signal, transmitting the first signal to the first DAC, splitting the second signal into a first and a second subsignal and transmitting the first subsignal to the second DAC and the second subsignal to the third DAC, the first subsignal corresponding to the real part of the second signal and the second subsignal corresponding to the imaginary part of the second signal; an IQ mixer configured for mixing an analog output signal of the second DAC and an analog output signal of the third DAC and a combiner for combining an analog output signal of the first DAC and an output signal of the IQ mixer.

A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. The analog crossbar array can be implemented in CMOS and memristors or a hybrid solution including a combination of CMOS and memristors.

A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. The analog crossbar array can be implemented in CMOS and memristors or a hybrid solution including a combination of CMOS and memristors.

An artificial intelligence processing device includes: a first variable-resistance nonvolatile storage element and a second variable-resistance nonvolatile storage element having different properties and provided on a single substrate. When successive applications of a voltage pulse with a same polarity and a same voltage are made, a proportion of an amount of change in conductance caused by a second application of the voltage pulse relative to an amount of change in conductance caused by a first application of the voltage pulse in the first variable-resistance nonvolatile storage element is less than a proportion of an amount of change in conductance caused by a second application of the voltage pulse relative to an amount of change in conductance caused by a first application of the voltage pulse in the second variable-resistance nonvolatile storage element.

It is provided a signal processing system, comprising at least a first, a second and a third digital-to-analog converter (DAC); a processing unit configured for splitting a sampled signal into a first and a second signal corresponding to different frequency portions of the sampled signal, transmitting the first signal to the first DAC, splitting the second signal into a first and a second subsignal and transmitting the first subsignal to the second DAC and the second subsignal to the third DAC, the first subsignal corresponding to the real part of the second signal and the second subsignal corresponding to the imaginary part of the second signal; an IQ mixer configured for mixing an analog output signal of the second DAC and an analog output signal of the third DAC and a combiner for combining an analog output signal of the first DAC and an output signal of the IQ mixer.