A display apparatus includes a display panel including a gate line and a data line, a controller generating a source output enable signal determining an output timing of a data voltage output to the data line, and a data driver including a signal changer, generating a final source output enable signal by using the source output enable signal, and randomly changing the output timing of the data voltage for each gate line by using the final source output enable signal.

A display device may include a display panel which displays an image based on a data voltage, a driving controller including a net power control setter which determines a scale factor for adjusting a gray scale of (N+1).sup.th frame data based on a load of N.sup.th frame data and a net power control reference value, where the driving controller generates a data signal based on input image data, and N is a natural number greater than or equal to 2, a data driver which converts the data signal into the data voltage and outputs the data voltage to the display panel, and a power supply voltage generator which senses a power supply current applied to the display panel in an N.sup.th frame and generates a power supply voltage based on a current level of the power supply current.

A display device can include a display panel including a display area in which sub-pixels are disposed, and a non-display area adjacent to the display area and in which a second pad portion is disposed, a printed circuit board including a first pad portion for outputting voltages to the display panel, and a circuit film including a first end connected to the first pad portion of the printed circuit board and a second end connected to the second pad portion of the display panel. The display device can further include an analog-to-digital converter to receive a voltage output from the first pad portion or the second pad portion through a line in the circuit film electrically connecting the first pad portion with the second pad portion, and output a value corresponding to the voltage input for detecting a bonding state of at least one internal component within the display device.

Disclosed is a display apparatus which may prevent a settling time from being changed when image data input to a source drive integrated circuit (IC) is changed, for voltage interpolation. The display apparatus includes a source drive integrated circuit (IC) configured to sequentially perform a first voltage interpolation and a second voltage interpolation at every horizontal period so as to drive a data line by using N bit image data including an M bit interpolation code and an N-M bit image code.

The disclosure relates to a disclosed display device and a display driving method. According to an embodiment, the disclosed display device may include a display panel having a first subpixel including a light emitting element and being connected to a sensing line in the display panel for sensing a characteristic value of the first subpixel; a gate driving circuit configured to supply a scan signal to the first subpixel through a gate line in the display panel; a data driving circuit configured to supply a data voltage to the first subpixel through a data line in the display panel; and a timing controller. The timing controller may be configured to: control the gate driving circuit; determine compensation data for compensating for a deviation in the characteristic value of the first subpixel based on a first sensing voltage, a second sensing voltage, and a third sensing voltage on the sensing line; and control the data driving circuit based on the compensation data.

The present disclosure provides a display panel and a display device. The display panel includes source driver chips. The source driver chips include charging compensation modules, and each of the charging compensation modules includes: a plurality of shift registers cascadely connected and configured to time-divisionally output a plurality of pulse signals, and a plurality of level shift circuits time-divisionally conducted in response to the plurality of the pulse signals to prevent the plurality of the level shift circuits in the source driver chips from outputting and generating a plurality electron currents at a same time, which would result in a superposition of current peaks and cause electromagnetic interference problems.

A first capacitance element provided corresponding to a bit D0, a second capacitance element provided corresponding to a bit D1, and a third capacitance element and a fourth capacitance element provided corresponding to a bit D2, and electrically coupled in parallel are included. An area S1 where electrodes of the first capacitance element overlap in plan view is smaller than half an area S2 where electrodes of the second capacitance element overlap in plan view, an area in which electrodes of the third capacitance element overlap in plan view is substantially the same as the area S2, and an area where electrodes of the fourth capacitance element overlap in plan view is substantially the same as the area S2.

A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

In a display device having an external compensation function, a decrease in compensation accuracy caused by coupling noise generated in a data signal line is prevented. An emission driver that applies a light-emission control signal (EM) to each of a plurality of light-emission control lines includes a shift register formed of a plurality of unit circuits. The shift register generates a light-emission control signal (EM) to be applied to each light-emission control line on the basis of a plurality of light-emission control clock signals (ECK1 to ECK4) outputted from a display control circuit. The display control circuit stops the outputs of the plurality of light-emission control clock signals (ECK1 to ECK4) throughout a current measurement period in which a current corresponding to the characteristic of the drive transistor is measured.

A first capacitance element provided corresponding to a bit D0, a second capacitance element provided corresponding to a bit D1, and a third capacitance element and a fourth capacitance element provided corresponding to a bit D2, and electrically coupled in parallel are included. An area S1 where electrodes of the first capacitance element overlap in plan view is smaller than half an area S2 where electrodes of the second capacitance element overlap in plan view, an area in which electrodes of the third capacitance element overlap in plan view is substantially the same as the area S2, and an area where electrodes of the fourth capacitance element overlap in plan view is substantially the same as the area S2.