An organic light emitting diode display device includes: a substrate including a plurality of sub-pixels classified into a plurality of horizontal pixel lines; a gate line and a sensing line spaced apart from each other on the substrate; a data line and a power line crossing the gate line and the sensing line and spaced apart from each other; and first and second reference lines supplying first and second reference voltages, respectively, and connected to adjacent two, respectively, of the plurality of horizontal pixel lines.

A pixel circuit and a display device including the pixel circuit are disclosed. The pixel circuit according to embodiments includes a first pixel circuit connected in parallel to an initialization voltage line to which an initialization voltage is applied, and including a first-first switch element connected to a first-first gate line and a first-second switch element connected to a first-second gate line; and a second pixel circuit connected in parallel to the initialization voltage line, and including a second-first switch element connected to a second-first gate line and a second-second switch element connected to a second-second gate line, and the first-second gate line and the second-first gate line are electrically connected.

A emitting display device can include a display panel including a plurality of pixels; a plurality of gate lines configured to supply gate signals to the pixels; and a plurality of stages connected to the plurality of gate lines, and configured to output gate pulses to a group of pixels connected to at least two gate lines among the plurality of gate lines for sensing a characteristic of each pixel among the group of pixels during a sensing period.

In an electro-optical device, pixel circuits are provided corresponding to an intersection between a scanning line in an i-th row and a data line in a k-th column in a display region, and an intersection between a scanning line and data line. The pixel circuit is brought into an optical state in accordance with a voltage of a data line when a scanning line is selected. In an odd frame period, in the i-th row selection period and the (i + 1)-th row, a data signal of a voltage corresponding to the i-th row and k-th column of data of the top image is output, and in an even frame period, in the i-th row selection period and the (i + 1)-th row, a data signal of a voltage corresponding to the (i + 1)-th row and the k-th column of data of the bottom image is output.

A display device includes a plurality of pixels connected to a plurality of first scan lines, a plurality of second scan lines, and a plurality of data lines, where the pixels are arranged in a plurality of rows, a plurality of first stages connected to the first scan lines, a plurality of second stages connected to the second scan lines, and a data driver connected to the data lines. Each of the first scan lines is connected to pixels arranged in a corresponding row among the rows. Each of the second scan lines is commonly connected to pixels arranged in corresponding 8h rows among the plurality of rows, where h is a natural number.

A display device includes a display panel including scan lines, first signal lines connected to the scan lines in a first pixel block, second signal lines connected to the scan lines in a second pixel block, third signal lines connected to the scan lines in a third pixel block; a first scan driver supplying a first output signal to the first signal lines based on a first sub-clock signal; a second scan driver supplying a second output signal to the second signal lines based on a second sub-clock signal; a third scan driver supplying a third output signal to the third signal lines based on and a third sub-clock signal; and a timing controller. Changes in pulse widths of the first to third output signals are different in one frame period.

A pixel circuit and a display device including the pixel circuit are disclosed. The pixel circuit according to embodiments includes a first pixel circuit connected in parallel to an initialization voltage line to which an initialization voltage is applied, and including a first-first switch element connected to a first-first gate line and a first-second switch element connected to a first-second gate line; and a second pixel circuit connected in parallel to the initialization voltage line, and including a second-first switch element connected to a second-first gate line and a second-second switch element connected to a second-second gate line, and the first-second gate line and the second-first gate line are electrically connected.

The present disclosure relates to the field of display technologies, and in particular, to a shift register circuit and a display device. The shift register circuit may include a plurality of GOAs for outputting scan signals to a plurality of pixel driving circuits and a plurality of EOAs for outputting control signals to the plurality of pixel driving circuits, where the GOAs and the EOAs are alternately arranged in a straight line.

A display panel and a driving method thereof are provided. The display panel includes a plurality of sub-pixels arranged in an array. The plurality of sub-pixels are divided into a plurality of units arranged along rows and columns, and the unit includes a plurality of the sub-pixels. Polarities of the sub-pixels in any two adjacent sub-units are different, a number of the sub-pixels in any one of the sub-units is less than or equal to 4, and a number of the sub-pixels in one of the sub-units that has a common boundary with the unit is less than or equal to 2.

A display panel and a driving method thereof are provided. The display panel includes a plurality of sub-pixels arranged in an array. The plurality of sub-pixels are divided into a plurality of units arranged along rows and columns, and the unit includes a plurality of the sub-pixels. Polarities of the sub-pixels in any two adjacent sub-units are different, a number of the sub-pixels in any one of the sub-units is less than or equal to 4, and a number of the sub-pixels in one of the sub-units that has a common boundary with the unit is less than or equal to 2.