A display device includes a display panel including a first display area; a second display area protruding in a first direction from the first display area; and a first non-display area adjacent to a side of the second display area. Each of the first display area and the second display area includes subpixels that display an image and scan lines electrically connected to the subpixels. The first non-display area includes dummy pixels; a common scan line electrically connected to the dummy pixels; load matching switch elements respectively disposed between the scan lines and the common scan line; and a load matching driving circuit that outputs load matching control signals to control turn-on and turn-off of the load matching switch elements.

A pixel circuit, a driving method for the pixel circuit, a display panel, and a display device, the pixel circuit includes a selecting module (01), a writing module (02), a driving module (03), and a light emitting element (OLED). When a high-luminance picture needs to be displayed, the selecting module (01) outputs the signal from the first power supply signal terminal (VDDH) to the second node (P2), so that the signal from the first power supply signal terminal (VDDH) drives the light emitting element (OLED) to emit light; when a low-luminance picture is to be displayed, the selecting module (01) outputs a signal from the second power supply signal terminal (VDDL) to the second node (P2), so that the signal from the second power source signal (VDDL) drives the light emitting element to emit light.

An array substrate has a display area and a bonding region. The display area includes a distal region, a proximal region, and a middle region therebetween. The array substrate includes a base, a common electrode located in the display area, a connecting lead disposed outside the distal region, a conductive frame at least partially surrounding the display area, and at least one first common signal line, at least one second common signal line and at least one third common signal line. The first common signal line, the second common signal line and the third common signal line are respectively coupled to portions of the common electrode located in the distal region, the proximal region and the middle region. The first common signal line is coupled to the connecting lead. The connecting lead and the portion of the common electrode located in the distal region are coupled to the conductive frame.

A display panel includes a pixel circuit, a driving circuit, and a clock signal line. The driving circuit is configured to provide a control signal to the pixel circuit. The clock signal line is configured to provide a clock signal for the driving circuit. A data refresh period of the pixel circuit includes a data writing stage and a holding stage. The holding stage includes N stages arranged in sequence, N≥1. When the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1. When the pixel circuit is operated in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal is a second frequency F2.

Disclosed is an electroluminescent display device using a variable refresh rate (VRR) mode. The purpose of the present disclosure is to reduce the occurrence of a difference in luminance at a time point of a refresh rate change, thereby preventing viewers from perceiving the variation of the refresh rate.

Provided are a display driving method and apparatus, and a display panel and an electronic device. The display driving method is applied to a display panel, and comprises: determining a first charging duration of each display point on the basis of a preset position, in a display panel, of each display point in the display panel; generating, according to the first charging duration of each display point, a display control signal corresponding to each display point; and adjusting a second charging duration of each display point according to the display control signal.

A low drop-out (LDO) regulator includes a power transistor, an error amplifier and a droop adjusting circuit. The power transistor regulates a driving voltage based on a gate voltage of a gate node to provide an output voltage at an output node. The error amplifier outputs the gate voltage by amplifying a voltage difference between a reference voltage and a feedback voltage proportional to the output voltage. The droop adjusting circuit is connected between the gate node and the output node, is coupled to the output voltage, and adjusts the gate voltage to compensate for a change of the output voltage based on a change of a load current which is provided to a load from the output node.

An electroluminescence display apparatus includes a display panel, including a pixel including a driving element and a light emitting device, and a panel driving circuit supplying the pixel with a first data voltage for a display driving operation and a display scan signal synchronized with the first data voltage in a vertical active period succeeding a first vertical blank period and maintaining the first data voltage in the pixel during a second vertical blank period succeeding the vertical active period, wherein a length of the first vertical blank period is fixed regardless of a variation of a frame frequency, and a length of the second vertical blank period varies based on the variation of the frame frequency.

A gamma reference voltage generator includes a first resistor string, black voltage setters, a selector, and a second resistor string. The first resistor string receives a first reference voltage and a second reference voltage. The black voltage setters extract a plurality of black candidate voltages from the first resistor string. The selector selects one of the black candidate voltages as a black gamma voltage based on a selection signal. The second resistor string receives a first voltage corresponding to one of the black candidate voltages and a second voltage extracted from the first resistor string. In addition, the gamma reference voltage generator includes gamma voltage setters that extract a plurality of gamma voltages from the second resistor string.

Provided are a display panel and display device. The display panel includes a driver circuit comprising a shift register that is N-stage cascaded; wherein the shift register comprises: a third control unit configured to receive a first voltage signal and generate an output signal in response to a signal of a third node, or receive a second voltage signal and generate an output signal in response to a signal of a second node; and a fourth control comprising a first capacitor and a first transistor, wherein a second plate of the first capacitor is connected to a drain of the first transistor, a source of the first transistor receives a first control signal, and a gate of the first transistor receives a second control signal.