The present application provides a GOA circuit and a display panel. In the GOA circuit, one of two GOA units of a same stage in GOA sub circuits at left and right sides of the display panel is deployed only with an all-on module and the other one of the two GOA units is deployed only with an all-off module. In such a way, both the number of the all-on modules and the number of the all-off modules required in the GOA unit are halved, thereby reducing the area occupied by the GOA circuit. It is beneficial for realizing a display panel with a narrow bezel.

Provided is a method for driving a display device, including n rows of sub-pixels; the method includes: driving the first frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on a rows, from the 1.sup.st to a.sup.th rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−a) rows, from the (a+1).sup.th to n.sup.th rows, of sub-pixels in a second darkness insertion sub-period driving a second frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on b rows, from the 1.sup.st to b.sup.th rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−b) rows, from the (b+1).sup.th to n.sup.th rows, of sub-pixels in a second darkness insertion sub-period.

A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

The present application discloses a cross voltage compensation method for a display panel, a display panel and a display device. The cross voltage compensation method includes steps of transmitting a preset voltage signal to in-plane data lines after scan of scanning lines of a last row of a current frame is completed and before scanning lines of a first row of a next frame are started, keeping all the scanning lines at a close state while transmitting the preset voltage signal to in-plane data lines, and keeping all the scanning lines at a close state after scan of scanning lines of a last row of a current frame is completed and before scanning lines of a first row of a next frame are started, that is, V-blank time.

Provided is a method for driving a display device including n rows of sub-pixels; the method includes: driving the first frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on a rows, from the 1.sup.st to a.sup.th rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−a) rows, from the (a+1).sup.th to n.sup.th rows, of sub-pixels in a second darkness insertion sub-period driving a second frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on b rows, from the 1.sup.st to b.sup.th rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−b) rows, from the (b+1).sup.th to n.sup.th rows, of sub-pixels in a second darkness insertion sub-period.

A display device, includes: a scan driver configured to sequentially supply scan signals having a turn-on level to the first scan line and the second scan line during a first period and to concurrently supply scan signals having a turn-on level to the first scan line and the second scan line during a second period after the first period, wherein: a mask period corresponds to a difference between a start point of the second period and a start point of the first period in a next frame period, a first frame period and a second frame period have different mask periods, a third frame period between the first frame period and the second frame period has a same mask period as the first frame period, and a fourth frame period between the first frame period and the second frame period has a same mask period as the second frame period.

The present application provides a GOA circuit and a display panel. In the GOA circuit, one of two GOA units of a same stage in GOA sub circuits at left and right sides of the display panel is deployed only with an all-on module and the other one of the two GOA units is deployed only with an all-off module. In such a way, both the number of the all-on modules and the number of the all-off modules required in the GOA unit are halved, thereby reducing the area occupied by the GOA circuit. It is beneficial for realizing a display panel with a narrow bezel.

A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, a data-writing module, and a compensation module, and a reset module. The driving module includes a driving transistor. The data-writing module is connected to a source of the driving transistor and configured to selectively provide a data signal for the driving transistor. The compensation module is connected between a gate and a drain of the driving transistor. The reset module is connected between the drain of the driving transistor and a reset signal terminal and configured to provide a reset signal for the gate of the driving transistor. The reset module is used as a bias module. An operating process of the pixel circuit includes a reset stage and a bias stage.

A gate driver includes a first shift register to supply a gate signal to a plurality of gate lines through output nodes, and a second shift register to supply the gate signal to the gate lines through output nodes. The gate signal is supplied from the first shift register to one side of an i-th gate line and supplied from the second shift register to the other side of the i-th gate line, then the gate signal is supplied from the second shift register to the other side of the i-th gate line, then the gate signal is supplied from the first shift register to one side of the i-th gate line, and then, the gate signal is supplied from the first shift register to one side of the i-th gate line and simultaneously supplied from the second shift register to the other side of the i-th gate line.

A device includes a display panel with a first end, a second end, a first side, and a second side. The display panel includes a rounded corner region located between the first end and the first side and a plurality of pixel circuits. The plurality of pixel circuits includes a first set of pixel circuits ending in the rounded corner region and a second set of pixel circuits ending in a straight region adjacent to the rounded corner region, the straight region located on the first side of the display panel. A voltage supply bus is configured to carry an electrical signal along the rounded corner region and the straight region. A supplementary voltage supply bus, electrically connected to the voltage supply bus, is configured to carry the electrical signal to the plurality of the first set of pixel circuits in the rounded corner region.