A display device comprises a display panel including a plurality of data lines, a plurality of gate lines, a plurality of subpixels, and a plurality of reference voltage lines electrically connected with the plurality of subpixels, each of the plurality of subpixels including a driving transistor and a light emitting element and a gate driving circuit configured to supply a gate signal to the plurality of gate lines, wherein there are three or more periods during which a voltage change slope of a reference voltage line electrically connected with any one subpixel of the plurality of subpixels is decreased and then restored while the gate driving circuit applies the gate signal of a turn-on level voltage to the any one subpixel, thereby reducing the voltage level of the high-potential driving voltage applied to the display panel, to the minimum.

Disclosed is a display device including a first output part, a second output part, a power supply circuit connected to input terminals of the first output part and the second output part, a first sensing part connected to an output terminal of the first output part, a second sensing part connected to an output terminal of the second output part, a first voltage output terminal connected to the first sensing part and the second sensing part, a plurality of pixels connected to the first voltage output terminal and configured to display an image, and a defect determination part controlling shutdown of the power supply circuit by comparing a first sensing value and a second sensing value, which are received from the first sensing part and the second sensing part, with a first reference value and a second reference value having a level lower than the first reference value.

A display device includes a display panel on which a plurality of sub-pixels are disposed; a timing controller configured to transmit an image control signal to a host system to receive image data from the host system; a data driving circuit configured to convert the image data transmitted from the timing controller into a data voltage and configured to supply the data voltage to the display panel; and a semi-off switching circuit configured to control the image control signal so that the image data is cut off from the host system during a semi-off period of a predetermined time from a time when an off monitoring signal is transmitted from the host system in response to the power off signal.

A pixel circuit and a display device including the same are disclosed. The pixel circuit includes a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to supply an electric current to a light emitting element; a first switch element discharging the second node; and a second switch element configured to supply a data voltage to the second node. The light emitting element and the first switch element are commonly connected to a VSS node to which a low-potential power supply voltage is applied.

A power voltage generator includes a first sensor, a second sensor, a comparator and a shutdown controller. The first sensor is configured to sense a first power voltage output node that outputs a first power voltage. The second sensor is configured to sense a second power voltage output node that outputs a second power voltage. The comparator is configured to compare a first sensing signal of the first sensor with a second sensing signal of the second sensor. The shutdown controller is configured to shut down the power voltage generator based on a comparison signal from the comparator.

The present invention provides a gate driver on array (GOA) circuit, a display panel, and a threshold voltage compensating method for a thin film transistor (TFT). The GOA circuit only includes five TFTs and achieves a super narrow bezel of a display panel, and uses a dual-gate electrode structure as the first thin film transistor (T1). Therefore, a threshold voltage (Vth) in the GOA circuit is controlled by a top gate (the top gate connected to a node in the GOA circuit) and a bottom gate (adjustable voltage source (VLS)). Specifically, when the Vth of the TFT negatively shifts overall, the bottom gate voltage can be adjusted negatively. When the Vth of the TFT positively shifts, the bottom gate voltage can be adjusted negatively to stabilize the GOA circuit, increase a lifespan thereof, reduce leakage of a first node (Q) such that the GOA circuit can output ultra-wide pulse signals.

The present invention provides a data processing device connected with an intermission driving. The data processing device achieves a satisfactory power saving while ensuring a high level of display quality of the display device. Upon detection of non-data update in a frame buffer, the host calculates a next refreshing timing based on driving information obtained from a liquid crystal display device (LCD), sets a timer for a timeout after a length of time representing the calculated result, and then the host and the LCD shift to Intermission State 1. Thereafter, when the timer times out to bring the host back to Normal State and a data update at the frame buffer is detected, data for refreshing an display image in the LCD is transferred from the host to the LCD. If the amount of time representing the calculated result is longer than a predetermined baseline, a shift is made to Intermission State 2 which provides greater power saving than Intermission State 1.

The present application provides a GOA circuit and a display panel. In the GOA circuit, one of two GOA units of a same stage in GOA sub circuits at left and right sides of the display panel is deployed only with an all-on module and the other one of the two GOA units is deployed only with an all-off module. In such a way, both the number of the all-on modules and the number of the all-off modules required in the GOA unit are halved, thereby reducing the area occupied by the GOA circuit. It is beneficial for realizing a display panel with a narrow bezel.

A control method of a power supply path includes detecting a plug-in state of a first connector through a configuration channel pin of the first connector; acquiring a plurality of rated voltages of a first power adaptor externally connected to the first connector and a rated current corresponding to each of the rated voltages; detecting a plug-in state of a second connector through a direct-current (DC) input pin of the second connector; acquiring a power quota of a second power adaptor externally connected to the second connector; selecting, from the plurality of rated voltages, the largest one that is not greater than an operating voltage, as a selected rated voltage; calculating a power quota of the selected rated voltage; and controlling a switching circuit to couple a power circuit to a power pin of one of the first and second connectors according to the two power quotas.

A display device includes a substrate including a first display area including main pixels and a second display area including auxiliary pixels and transmissive portions; a camera module under the substrate to overlap the second display area in a thickness direction and including an image sensor; a control circuit board on the substrate and including a timing controller; and a main processor which provides an image signal to the timing controller. The camera module is directly connected to the control circuit board through a connection unit.