A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

A display apparatus of the present disclosure includes: an image detection unit that determines whether an empty second subframe is present in input image data, in addition to a first subframe that displays an image; a correction image generation unit that generates correction image data for correcting the input image data; a control unit that performs control to display the correction image data generated by the correction image generation unit during the period of the second subframe, when the image detection unit detects that the second subframe is present in the input image data; and a display panel that includes a light modulation device provided for each pixel, and modulates irradiation light from a light source, on the basis of input image data including the correction image data.

A display apparatus of the present disclosure includes: an image detection unit that determines whether an empty second subframe is present in input image data, in addition to a first subframe that displays an image; a correction image generation unit that generates correction image data for correcting the input image data; a control unit that performs control to display the correction image data generated by the correction image generation unit during the period of the second subframe, when the image detection unit detects that the second subframe is present in the input image data; and a display panel that includes a light modulation device provided for each pixel, and modulates irradiation light from a light source, on the basis of input image data including the correction image data.

A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

A display device is provided. The display device comprises a display panel including a plurality of signal pads and one or more dummy pads, and at least one flexible wiring board providing signals to the signal pads, wherein a maximum bias period of signals provided to a pair of adjacent signal pads with at least one dummy pad interposed therebetween is longer than a maximum bias period of signals provided to a pair of adjacent signal pads with no dummy pad disposed therebetween.

A gate driver includes a stage configured to output a gate signal, the stage including an input part configured to control a voltage of a first node and a voltage of a second node based on signals supplied to a first input terminal and a second input terminal, an output part configured to supply a voltage of a first power source or a voltage of a second power source as the gate signal to an output terminal based on a voltage of a third node and a voltage of a fourth node, a first signal processing part configured to supply the voltage of the second power source to the fourth node based on the voltage of the first node, or to electrically connect the second node and the fourth node through a fifth node based on a signal supplied to a third input terminal, and a second signal processing part including a first transistor connected between the third node and a sixth node to control the voltage of the third node based on an operation of the first transistor.

Disclosed are a signal processing device and an image display apparatus including the same. The signal processing device includes an amplifier to perform amplification based on an input differential signal, an output driver to output an audio output signal based on an output signal from the amplifier, a reference voltage output device to output a reference voltage in response to power ON, a pre-output driver configured to pre-compensate for an offset voltage and output a compensation signal, based on an output signal from the amplifier after the power ON, and a first switching device disposed between an output terminal of the output driver and an output terminal of the pre-output driver, wherein the output driver operates after the first switching device is turned on in response to the power ON. Accordingly, pop noise and harmonic distortion in case in which power is turned on may be reduced.

A display apparatus of the present disclosure includes: an image detection unit that determines whether an empty second subframe is present in input image data, in addition to a first subframe that displays an image; a correction image generation unit that generates correction image data for correcting the input image data; a control unit that performs control to display the correction image data generated by the correction image generation unit during the period of the second subframe, when the image detection unit detects that the second subframe is present in the input image data; and a display panel that includes a light modulation device provided for each pixel, and modulates irradiation light from a light source, on the basis of input image data including the correction image data.