A pixel that emits light at brightness corresponding to the amount of a driving current regardless of a threshold voltage of a driving transistor, and secure sufficient compensation time by separating an operation of compensating for the threshold voltage of the driving transistor and an operation of writing a data signal, and a display apparatus including the pixel.

A pixel circuit includes a data writing sub-circuit and a leakage prevention sub-circuit. The data writing sub-circuit is coupled to a first scan signal terminal, a data signal terminal and a light-emitting control sub-circuit, and is configured to: in a data writing period, store a light-emitting compensation signal in response to a gate scan signal from the first scan signal terminal and a data signal from the data signal terminal; and in a light-emitting period, assist in controlling the light-emitting control sub-circuit to be turned on according to the light-emitting compensation signal. The leakage prevention sub-circuit is coupled to the data writing sub-circuit and an auxiliary voltage terminal that is configured to provide to a constant voltage, and is configured to: in the data writing period, store another light-emitting compensation signal; and in the light-emitting period, inhibit leakage of the data writing sub-circuit according to the another light-emitting compensation signal.

A display panel includes a sub-pixel array, gate lines, first data lines, second data lines, a pixel control circuit and a time-division multiplexing circuit. The sub-pixel array includes a plurality of sub-pixels arranged in rows and columns. Sub-pixels in a same row are coupled to the pixel control circuit through at least one gate line. Sub-pixels located in odd-numbered rows in sub-pixels in a same column are coupled to a first data line, and sub-pixels located in even-numbered rows in the sub-pixels in the same column are coupled to a second data line. The time-division multiplexing circuit is coupled to the plurality of first data lines, the plurality of second data lines, and a data signal terminal. The time-division multiplexing circuit is configured to electrically connect the data signal terminal to the first data lines and the second data lines in a time-division manner.

A display device comprises a display panel including a plurality of data lines, a plurality of gate lines, a plurality of subpixels, and a plurality of reference voltage lines electrically connected with the plurality of subpixels, each of the plurality of subpixels including a driving transistor and a light emitting element and a gate driving circuit configured to supply a gate signal to the plurality of gate lines, wherein there are three or more periods during which a voltage change slope of a reference voltage line electrically connected with any one subpixel of the plurality of subpixels is decreased and then restored while the gate driving circuit applies the gate signal of a turn-on level voltage to the any one subpixel, thereby reducing the voltage level of the high-potential driving voltage applied to the display panel, to the minimum.

A display device comprises a display panel including a plurality of data lines, a plurality of gate lines, a plurality of subpixels, and a plurality of reference voltage lines electrically connected with the plurality of subpixels, each of the plurality of subpixels including a driving transistor and a light emitting element and a gate driving circuit configured to supply a gate signal to the plurality of gate lines, wherein there are three or more periods during which a voltage change slope of a reference voltage line electrically connected with any one subpixel of the plurality of subpixels is decreased and then restored while the gate driving circuit applies the gate signal of a turn-on level voltage to the any one subpixel, thereby reducing the voltage level of the high-potential driving voltage applied to the display panel, to the minimum.

A display device includes a light emitting element including an anode, a cathode, and a light emitting layer between the anode and the cathode, a first transistor connected between the anode and a first power line, the first transistor may be switched by a voltage of a node, a second transistor connected between the first transistor and a data line, the second transistor may be switched by a write scan signal, a third transistor connected between the node and the anode, the third transistor may be switched by a compensation scan signal, a fourth transistor connected between the node and an initialization line, the fourth transistor may be switched by an initialization scan signal, an insulating layer on the first to the fourth transistors, and a light blocking pattern protruding from the insulating layer, the light blocking pattern being adjacent to the third transistor and the fourth transistor.

The display apparatus includes a substrate including an auxiliary circuit area and an auxiliary display area, an auxiliary pixel circuit on the auxiliary circuit area, an auxiliary display element on the auxiliary display area, and a connection line extending from the auxiliary circuit area to the auxiliary display area and configured to connect the auxiliary pixel circuit to the auxiliary display element. The connection line includes a first sub-line and a second sub-line which are on different layers, and the first sub-line is electrically connected to the second sub-line through a contact portion.

The display apparatus includes a substrate including an auxiliary circuit area and an auxiliary display area, an auxiliary pixel circuit on the auxiliary circuit area, an auxiliary display element on the auxiliary display area, and a connection line extending from the auxiliary circuit area to the auxiliary display area and configured to connect the auxiliary pixel circuit to the auxiliary display element. The connection line includes a first sub-line and a second sub-line which are on different layers, and the first sub-line is electrically connected to the second sub-line through a contact portion.

A display device includes a display panel, a data driving circuit, and a timing controller, wherein the display panel includes a plurality of gate lines to which a scan signal is applied, a plurality of data lines to which a data voltage is applied, a plurality of reference voltage lines to which a reference voltage is applied, and a plurality of subpixels, wherein the data driving circuit senses a voltage on one reference voltage line selected from the plurality of reference voltage lines in a first detecting period and a second detecting period having different voltage detecting paths, and wherein the timing controller controls the data driving circuit, and determining whether or not the reference voltage line is abnormal using a sensing voltage detected from the reference voltage line.

A display device includes a display panel, a data driving circuit, and a timing controller, wherein the display panel includes a plurality of gate lines to which a scan signal is applied, a plurality of data lines to which a data voltage is applied, a plurality of reference voltage lines to which a reference voltage is applied, and a plurality of subpixels, wherein the data driving circuit senses a voltage on one reference voltage line selected from the plurality of reference voltage lines in a first detecting period and a second detecting period having different voltage detecting paths, and wherein the timing controller controls the data driving circuit, and determining whether or not the reference voltage line is abnormal using a sensing voltage detected from the reference voltage line.