A perpendicular magnetic recording (PMR) writer is disclosed wherein an insulation layer is formed between a top yoke (TY) and an uppermost (PP3) trailing shield to electrically isolate the main pole (MP) from a trailing loop for magnetic flux return. One or both of a first non-magnetic (NM) metal layer and a second NM metal layer are formed between the MP tip and a hot seed layer and side shields, respectively, to form an electrical path that is in parallel to that of a dynamic fly height (DFH) heater circuit. MP tip protrusion is enhanced and writability is improved especially for track widths <40 nm, and is tunable by the volume of the first and second NM layer, and the composition of the NM metals. Existing writer pad layouts may be employed and there is no additional cost to PMR backend processes.

A magnetic recording write head includes a spin torque oscillator (STO) between a seed layer disposed on a write pole and trailing shield. The seed layer has a cross-track width greater than the width of the STO and a depth in a direction orthogonal to the disk-facing surface of the write pole greater than the depth of the STO. A first insulating refill layer is formed on the sides of the seed layer and STO, and a second insulating refill layer in contact with the first refill layer has a thermal conductivity greater than that of the first refill layer. When current is passing through the STO, the seed layer spreads the current to reduce heating of the write pole and STO, and the bilayer refill material facilitates the transfer of heat away from the write pole and STO.

A magneto-resistive (MR) sensor protection circuit is disclosed, for the protection of an MR sensor. The MR sensor may have a safe operating voltage range, a normal operating voltage range within the safe operating voltage range, and two terminals coupled to a read channel circuit, including a positive terminal and a negative terminal. The MR sensor protection circuit may have positive and negative protection threshold voltage ranges. The MR sensor protection circuit may also have a plurality of N-channel field-effect transistors (NFETs) that are coupled to the positive terminal and to the negative terminal, and configured to, in response to a voltage between the two terminals being within either the positive or the negative protection threshold voltage range, limit the voltage between the terminals by shunting current between the positive terminal and the negative terminal.