A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.

Provided is a method of a generating a skyrmion. The method includes a step of preparing a magnetic multilayer system and a step of generating a skyrmion at a temperature of 400° C. or higher by adjusting the magnetic anisotropy value and the magnetization value of the magnetic multilayer system.

There is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.

In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

A memory device includes; a memory cell array including memory cells, a row decoder selecting a word line in response to a received address, and control logic including a sensing capacitor having a size proportional to a size of a word line capacitor associated with the selected word line. The control logic measures line resistance of the selected word line by precharging the selected word line, performing a charge sharing operation between the selected word line and the sensing capacitor following the precharging of the selected word line, and measuring a voltage of the sensing capacitor following the performing of the charge sharing operation.

Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component may be activated, a reference voltage may be applied to the sense component, and the first switching component may then be deactivated. In some examples, a voltage offset may be measured across both the first and the second capacitor.

A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

A drive circuit, a method for driving the drive circuit and a memory are provided. The drive circuit includes a word line drive circuit and a first control circuit. The word line drive circuit includes an input terminal, an output terminal and at least one N-type transistor. The word line drive circuit is configured to provide an output signal to the output terminal according to an input signal received by the input terminal. The first control circuit is configured to pull down, in response to the input signal being a first control signal, a voltage of a substrate terminal of the at least one N-type transistor in the word line drive circuit, to reduce a leakage current of the at least one N-type transistor.

A semiconductor device capable of changing a data programming process in a simple manner according to a situation is provided. The semiconductor device includes a plurality of memory cells, a programming circuit for supplying a programming current to the memory cell, and a power supply circuit for supplying power to the programming circuit. The power supply circuit includes a charge pump circuit for boosting the external power supply, a voltage of the external power supply according to the selection indication, and a selectable circuit capable of switching the boosted voltage boosted by the charge pump circuit. The control circuit further includes a control circuit for executing data programming processing by the programming circuit by switching the selection indication.

A method of forming a radially anisotropic toroidal magnetic core includes providing apparatus having a first magnet for providing a radial magnetic field extending across a cavity from an axial spindle to a surrounding second magnetic element, placing a substrate in the cavity, the substrate having a hole fitting around the head of the spindle; and sputter-depositing a film of ferromagnetic material onto the substrate. In an embodiment, the spindle is magnetically coupled to a first pole of the first magnet, the second magnetic element is coupled to a second pole of the first magnet, and a thermally conductive, nonmagnetic, insert separates the spindle and the second magnetic element.