Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.

An electronic device may include a first electrode, a first piezoelectric layer electrically coupled to the first electrode, a first magnetostrictive layer above the first piezoelectric layer, a first tunnel barrier layer above the first magnetostrictive layer, and a ferromagnetic layer above the first ferroelectric layer. The electronic device may further include a second electrode electrically coupled to the ferromagnetic layer a second tunnel barrier layer above the ferromagnetic layer, a second magnetostrictive layer above the second tunnel barrier layer, a second piezoelectric layer above the second magnetostrictive layer, and a third electrode electrically coupled to the second piezoelectric layer. The first piezoelectric layer may be strained responsive to voltage applied across the first and second electrodes, and the second piezoelectric layer may be strained responsive to voltage applied across the second and third electrodes.

There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.

According to one embodiment, a magnetic device includes first and second conductive portions, first and second stacked bodies, and a controller. The first conductive portion includes first to third region. The third region is between the first and second regions. The first stacked body includes first and second magnetic layers. The second magnetic layer is between the third region and the first magnetic layer. The second conductive portion includes fourth to sixth regions. The sixth region is between the fourth and fifth regions. The second stacked body includes third and fourth magnetic layers. The fourth magnetic layer is between the sixth region and the third magnetic layer. The first stacked body is configured to be in a first low or high electrical resistance state. The second stacked body is configured to be in a second low high electrical resistance state.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

Disclosed is a content addressable memory device including a memory cell array including a plurality of memory cells, each of which has a ferroelectric tunnel field effect transistor (FeTFET), and a match amplifier connected to the plurality of memory cells through a plurality of match lines. The FeTFET includes a first doped region including a first conductivity type, a second doped region including a second conductivity type different from the first conductivity type, a channel region formed between the first doped region and the second doped region, and a gate formed on the channel region and including a ferroelectric layer.

A memory package includes; a first memory chip including first memory pads, and a buffer chip including first buffer pads respectively connected with the first memory pads and second buffer pads connected with an external device. The buffer chip respectively communicates signals received via the second buffer pads to the first buffer pads in response to a swap enable signal having a disabled state, and the buffer chip swaps signals received via the second buffer pads to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads in response to the swap enable signal having an enabled state.

An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL. Improved memory circuits are enabled by utilizing TFTs to improve density and access in a three dimensional circuit design which minimizes die area. Improved I/O is enabled by eliminating the area on the surface of the semiconductor dedicated to I/O and allowing many times the number of I/O available. Improved speed and lower power are also enabled by the shortened metal routing lines and reducing leakage.

A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.