A method includes forming a plurality of first line-shaped mask patterns over a substrate including a memory cell region and an array edge region; forming a plurality of second line-shaped mask patterns over the plurality of first line-shaped mask patterns; removing first portions from the plurality of first line-shaped mask patterns in the memory cell region to leave a plurality of island-shaped mask patterns above the memory cell region; removing second portions from the plurality of first line-shaped mask patterns in the array edge region to leave a holes-provided mask pattern above the array edge region; forming a mask pattern which includes a plurality of holes provided on portions; and forming, with the mask pattern which includes the plurality of holes, a plurality of contact holes in the array edge region to provide a plurality of contact electrodes connected to a plurality of word-lines.

A capacitor structure, a semiconductor memory device including the same, a method for fabricating the same, and a method for fabricating a semiconductor device including the same are provided. The capacitor structure includes a lower electrode, an upper electrode, and a capacitor dielectric film which is interposed between the lower electrode and the upper electrode, wherein the lower electrode includes an electrode film including a first metal element, and a doping oxide film including an oxide of the first metal element between the electrode film and the capacitor dielectric film, and the doping oxide film further includes a second metal element including at least one of Group 5 to Group 11 and Group 15 metal elements, and an impurity element including at least one of silicon (Si), aluminum (Al), zirconium (Zr) and hafnium (Hf).

The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of vertical sense lines coupled to each of the plurality of tiers. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line and configured to electrically couple the respective vertical sense line to a horizontal sense line. The memory device can also comprise a semiconductor under the array (SuA) circuitry, comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

An apparatus includes: a semiconductor substrate; an isolation region in the semiconductor substrate, the isolation region including an isolation trench filled with an insulating material therein; a plurality of island-shaped active regions in the semiconductor substrate surrounded by the isolation region; and a buried word-line having a bottom, the buried word-line at least passing across the isolation region between the plurality of active regions; wherein the isolation trench includes upper, middle and lower portions, each of the upper and lower portions has a substantially flat surface and the middle portion has a bulged surface.

Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

An apparatus includes a semiconductor substrate; an access transistor including channel, source and drain regions arranged in a vertical direction to the semiconductor substrate and a gate-electrode facing to the channel region; a storage capacitor coupled to one of the source and drain regions; a bit-line coupled to the other of the source and drain regions; and a pull-out-electrode connected to the bit-line; wherein surfaces of the source and drain regions and the pull-out-electrode on the bit-line side is arranged at substantially the same height from the upper surface of the semiconductor substrate.

A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.