An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.

Methods and systems for testing memory systems are disclosed. A refresh rate for a test system including a number of memory devices may be controlled based on estimated power scenario of a memory system design. In response to performance of a number of refresh operations on the memory devices and based on the refresh rate, one or more conditions of the test system may be monitored to generate estimated performance data for the memory system design.

A processing device of a memory sub-system is configured to determine a current refresh frequency associated with the memory device, the current refresh frequency specifying a rate of performing refresh operations on data stored at the memory device; compute an updated refresh frequency by updating the current refresh frequency based on a criterion reflecting a result of comparing one or more operating parameters of the memory device to their respective threshold values; and perform a refresh operation on data stored at the memory device according to the updated refresh frequency.

A method can include, in response to a power supply voltage transition, setting a temperature window to a first temperature range by operation of a temperature circuit formed on a semiconductor device. In response to a temperature of the semiconductor device being determined to be outside of the first temperature range, changing the temperature range of the temperature window until the temperature of the semiconductor device is determined to be within the temperature window.

According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of groups, each including a plurality of memory cells. The memory controller is configured to determine whether to execute a refresh process for a first group based on whether a first temperature in a write process for the first group and a second temperature after the write process for the first group satisfy a first condition.

Provided are electronic devices and methods for power reduction in systems with multiple memory ranks. The electronic device includes a memory system including first and second memory ranks and a memory controller connected to the memory system and configured to control power of the memory system. The memory controller being configured to cause the first memory rank to enter an idle power down (IPD) state during memory access in which a data toggle time without a data bubble is equal to or greater than an IPD minimum gain duration in another bank access for the second memory rank.

Disclosed herein is a method for controlling a refresh period of an extension memory pool. The method includes collecting information about each of preset unit DRAM cell sets of an extension memory pool, setting an initial refresh period for each of the DRAM cell sets, and adjusting the refresh period based on the information collected from the DRAM cell sets.

A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.

A load control device may include a semiconductor switch, a control circuit, and first and second terminals adapted to be coupled to a remote device. The load control device may include a first switching circuit coupled to the second terminal, and a second switching circuit coupled between the first terminal and the second terminal. The control circuit may be configured to render the first switching circuit conductive to conduct a charging current from an AC power source to a power supply of the remote device during a first time period of a half-cycle of the AC power source, and further configured to render the first and second switching circuits conductive and non-conductive to communicate with the remote device via the second terminal during a second time period of the half-cycle of the AC power source.