Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. The second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. The charge storage structure is located on a level of the apparatus between the first and second levels.

A refresh counter circuit, a refresh counting method and a semiconductor memory are provided. The refresh counter circuit includes: a first signal generator that is configured to generate a first carry signal according to each of refresh pulse signals generated by a received refresh command; a second signal generator that is configured to generate a second carry signal according to a last refresh pulse signal generated by the received refresh command; a first counter that is configured to perform signal inversion according to the first carry signal and generate a first output signal; and a second counter that is configured to count the refresh command according to the second carry signal and generate a second output signal; where the refresh command generates at least two refresh pulse signals.

A refresh counter circuit, a refresh counting method and a semiconductor memory are provided. The refresh counter circuit includes: a first signal generator that is configured to generate a first carry signal according to each of refresh pulse signals generated by a received refresh command; a second signal generator that is configured to generate a second carry signal according to a last refresh pulse signal generated by the received refresh command; a first counter that is configured to perform signal inversion according to the first carry signal and generate a first output signal; and a second counter that is configured to count the refresh command according to the second carry signal and generate a second output signal; where the refresh command generates at least two refresh pulse signals.

A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

A digital signal processing device includes a control unit that performs control to alternately burst transfer burst length audio data in a first half area of a first buffer memory and burst length audio data in a second half area of the first buffer memory to a DRAM, in which the control unit performs control to burst transfer the burst length audio data in the first half area of the first buffer memory to the DRAM while writing audio data one word at a time to the second half area of the first buffer memory in sequence and performs control to burst transfer the burst length audio data in the second half area of the first buffer memory to the DRAM while writing audio data one word at a time to the first half area of the first buffer memory in sequence.