A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line; during the write operation after the page erase operation, the positive hole group is formed in the channel semiconductor layer by an impact ionization phenomenon by controlling voltages applied to the word line, the drive control line, the source line, and the bit line; and an applied voltage/applied voltages of one or both of the word line and the drive control line is/are lowered with drops in a first threshold voltage of the first gate conductor layer and a second threshold voltage of the second gate conductor layer.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line; during the write operation after the page erase operation, the positive hole group is formed in the channel semiconductor layer by an impact ionization phenomenon by controlling voltages applied to the word line, the drive control line, the source line, and the bit line; and an applied voltage/applied voltages of one or both of the word line and the drive control line is/are lowered with drops in a first threshold voltage of the first gate conductor layer and a second threshold voltage of the second gate conductor layer.

Methods, systems, and devices for activate commands for memory preparation are described. A memory device may receive an activate command for a row of a memory bank in the memory device. The activate command may include an indicator that indicates a type of an access operation associated with the activate command. The memory device may perform, based on the type of the access operation, an operation to prepare the memory device for the access operation. The memory device may then receive an access command for the access operation after performing the operation to prepare the memory device for the access operation.

A memory access operation performed on a first memory unit of a memory device is detected. A counter associated with the first memory unit is modified. It is determined that the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a margin of an average number of memory access operations. A refresh operation is performed on a second memory unit.

A memory access operation performed on a first memory unit of a memory device is detected. A counter associated with the first memory unit is modified. It is determined that the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a margin of an average number of memory access operations. A refresh operation is performed on a second memory unit.

A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.