A current operating characteristic value of a unit of the memory device is identified. An operating characteristic threshold value is identified from a set of operating characteristic thresholds, where the current operating characteristic value satisfies an operating characteristic threshold criterion that is based on the operating characteristic threshold value. A set of write-to-read (W2R) delay time thresholds that corresponds to the operating characteristic threshold value is identified from a plurality of sets of W2R delay time thresholds. Each of the W2R delay time thresholds in the set is associated with a corresponding read voltage level. A W2R delay time threshold associated with a W2R delay time threshold criterion is identified from the set of W2R delay time thresholds, where the W2R threshold criterion is satisfied by a current W2R delay time of the memory sub-system. A read voltage level associated with the identified W2R delay time threshold is identified.

Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.

The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to count a number of program operations performed on the memory cells of the memory during operation of the memory, and increase a magnitude of a current used to sense a data state of the memory cells of the memory upon the count of the number of program operations reaching a threshold count.

Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.

A control method to operate a memory device, a control method to operate a memory system and a control system are provided. The control method includes providing a first voltage to a memory device for accessing a memory element of the memory device; obtaining an aging information of the memory device; and providing a second voltage to the memory device according to the aging information, wherein the first voltage and the second voltage are reverse biased voltages.

A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

According to one embodiment, there is provided a memory system including a non-volatile memory and a controller. The non-volatile memory includes a plurality of physical blocks. The controller is connected to any of the plurality of physical blocks via a plurality of channels. The controller is configured to construct a plurality of logical blocks and, read or write data from or into any of the plurality of logical blocks constructed. The logical blocks are management units in which any of the physical blocks is grouped across the plurality of channels. The controller is configured to construct the plurality of logical blocks so that a first number of defective blocks and a second number of pseudo defective blocks for shortfall defective blocks with respect to a target number of defective blocks are distributed into the plurality of logical blocks.

A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.