Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.

An elementary cell includes a device and a non-volatile resistive memory mounted in a series, the device including an upper selector electrode, a lower selector electrode, a layer made up of a first active material, referred to as an active selecting layer, the device being intended to form a volatile selector; the memory including an upper memory electrode, a lower memory electrode, a layer made of at least a second active material, referred to as an active memory layer, the active selecting layer being in a conductive crystalline state and the memory being in a very strongly resistive state that is more resistive than the strongly resistive state of the memory.

A physically unclonable function (PUF) device includes first and second inverters, each of which includes a common gate node and a common drain node. The common drain node of the first inverter is electrically connected to the common gate node of the second inverter. The PUF device also includes a common output node, a first resistive memory device (RMD) electrically connected to the common drain node of the first inverter and the common output node, and a second RMD electrically connected to the common drain node of the second inverter and the common output node.

A neuromorphic hardware apparatus based on a resistive memory array includes a resistive memory array in which a plurality of synaptic resistor elements are arranged. Each synaptic resistor element is changed in its resistance value depending on a voltage pulse applied thereto and stores the resistance value for a predetermined time. The apparatus also includes a neuron circuit configured to receive an output signal from the resistive memory array and to output a voltage signal to another resistive memory array. The neuron circuit includes a temperature compensation unit, which compensates for an output voltage of the resistive memory array on the basis of an operating temperature of the resistive memory array. Even when a resistive memory array outputs an abnormal output depending on an operating temperature, by compensating a neuron circuit for an input value, it is possible to prevent an operation error from occurring.

A memory device includes at least one bit line, at least one word line, and at least one memory cell. The memory cell includes a first transistor, a plurality of data storage elements, and a plurality of second transistors corresponding to the plurality of data storage elements. The first transistor includes a gate electrically coupled to the word line, a first source/drain, and a second source/drain. Each data storage element among the plurality of data storage elements and the corresponding second transistor are electrically coupled in series between the first source/drain of the first transistor and the bit line.

Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

A semiconductor memory apparatus may include a memory bank, a global buffer array, and an input and output circuit. The memory bank includes a local data circuit, and the global buffer array includes a global data circuit. The local data circuit is operably coupled to the global data circuit. The global buffer array may be operably coupled to the input and output circuit. The memory bank is disposed in a core region, and the global buffer array and the input and output circuit may be disposed in a peripheral region separated from the core region.

Various embodiments provide methods for configuring a phase-change random-access memory (PCRAM) structures, such as PCRAM operating in a single-level-cell (SLC) mode or a multi-level-cell (MLC) mode. Various embodiments may support a PCRAM structure being operating in a SLC mode for lower power and a MLC mode for lower variability. Various embodiments may support a PCRAM structure being operating in a SLC mode or a MLC mode based at least in part on an error tolerance for a neural network layer.

Systems are provided for implementing a hardware accelerator. The hardware accelerator emulate a stochastic neural network, and includes a first memristor crossbar array, and a second memristor crossbar array. The first memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The second memristor crossbar array is coupled to the first memristor crossbar array and programmed to introduce noise signals into the neural network. The noise signals can be introduced such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values.

In one example, a device to process analog sensor data is described. For example, a device may include at least one analog sensor to generate a first set of analog voltage signals and a crossbar array including a plurality of memristors. In one example, the crossbar array is to receive an input vector of the first set of analog voltage signals, generate an output vector comprising a second set of analog voltage signals that is based upon a dot product of the input vector and a matrix comprising resistance values of the plurality of memristors, detect a pattern of the output vector, and activate a processor upon a detection of the pattern.