A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data .

Memory devices and methods for operating the same are provided. Generally, the device includes an array of multibit-memory-cells, each operable to store multiple bits in separate locations of a charge-trapping layer, and control-circuitry coupled to the array. The control-circuitry is operable read 1st and 2nd bit values of each cell individually based on generated first and second sensed currents, where the first and second sensed currents correspond to charges trapped in first and second bit locations. The control-circuitry executes an algorithm based on the first and second sensed currents and determines a logic state of the cell. In one embodiment, the control-circuitry averages the sensed currents, and compares this to a reference current to determine the logic state. In another, the 2nd bit value is a complement of the 1st, and the control-circuitry compares the currents to determine the logic state without use of a reference current.

A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor and a second transistor. Gates of the first and second transistors are coupled to a corresponding first search line and a corresponding second search line.

Control logic in a memory device cause a programming pulse to be applied to a set of wordlines including a first set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, where a set of electrons are injected into a first set of gate regions, a second set of gate regions, and a set of inter-cell regions of a charge trap (CT) layer of the memory device. The control logic executes a first erase cycle on the first set of even-numbered wordlines to remove a first subset of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines. The control logic executes a second erase cycle on the second set of odd-numbered wordlines to remove a second subset of electrons from the second set of gate regions corresponding to the second set of even-numbered wordlines.

Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

To determine whether or not to data is compressed at a timing when a non-volatile memory device receives the data from a host apparatus. A storage controller transmits a specified logical address range, an update frequency level of the specified logical address range, and specified data to a device controller. On the basis of the update frequency level of the specified logical address range, the device controller determines whether the specified data is compressed or not. When determination is made that the specified data is compressed, the device controller compresses the specified data to generate compressed data, and writes the compressed data into a non-volatile memory. When determination is made that the specified data is not compressed, the device controller writes the specified data into the non-volatile memory.

Memory cells having isolated charge sites and methods of fabricating memory cells having isolated charge sites are described. In an example, a nonvolatile charge trap memory device includes a substrate having a channel region, a source region and a drain region. A gate stack is disposed above the substrate, over the channel region. The gate stack includes a tunnel dielectric layer disposed above the channel region, a first charge-trapping region and a second charge-trapping region. The regions are disposed above the tunnel dielectric layer and separated by a distance. The gate stack also includes an isolating dielectric layer disposed above the tunnel dielectric layer and between the first charge-trapping region and the second charge-trapping region. A gate dielectric layer is disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer. A gate electrode is disposed above the gate dielectric layer.

A method for operating artificial neural network with nonvolatile memory device having at least one artificial neural nonvolatile memory network. The forgoing artificial neural nonvolatile memory network (ANN) comprises M×N numbers nonvolatile memory cells that are arranged to form a memory array, and the nonvolatile memory cell can be a non-overlapped implementation (NOI) MOSFET, a RRAM element, a PCM element, a MRAM element, or a SONOS element. By applying this novel method to the ANN, it is able to perform feedforward and recurrent operations in the M×N numbers of nonvolatile memory devices in the ANN, so as to adjust or correct the weights stored in the M×N numbers of nonvolatile memory devices.