A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks, each block having a plurality of pages, each page having a plurality of memory cells, wherein the plurality of memory block includes an SLC (Single Level Cell) block and an MLC (Multi-Level Cell) block; and a controller suitable for programming input data transmitted from a host to both the SLC block and the MLC block in response to a first program command, and invalidating the input data programmed in the SLC block at a time point when the program operation for the MLC block is completed, when the memory system is powered on after an SPO (Sudden Power-Off) occurred while the program operation was performed on both the SLC block and the MLC block, the controller may perform a recovery operation to the MLC block based on valid data programmed in the SLC block.

A storage device includes a controller configured to control a non-volatile memory device(s) having a plurality of memory blocks therein. The controller includes secure erase control logic configured to: (i) control secure erase operations on the plurality of memory blocks in response to a secure erase request received from a host, and (ii) set flags corresponding to the plurality of memory blocks such that a first flag corresponding to a first memory block, which has undergone at least two of the secure erase operations, has a first value. Adaptive control logic is provided, which is configured to change at least one operating condition associated with a write operation and/or read operation directed at the first memory block, in response to detecting that the first flag has the first value.

Various embodiments provide for erasing of one or more partially-programmed memory units of a memory device. In particular, various embodiments provide for monitoring (e.g., tracking) of partial program/erase cycles for a memory unit (e.g., block) of a memory device, and performing an erasure of the memory unit based on the monitoring.

A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.

A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes. The memory cells are connected in series between a drain-side select gate transistor on a drain-side and connected to one of a plurality of bit lines and a source line on a source-side. A control means is configured to apply a first and a second select gate voltage to the drain-side select gate transistor while applying a predetermined source line voltage to the source line of selected ones of the memory holes in a predetermined grouping and a read level voltage to at least one of the word lines associated with the predetermined grouping. The control means counts the memory cells conducting during each of a first and a second read operation and adjusts the predetermined source line voltage accordingly.

Various embodiments provide for erasing of one or more partially-programmed memory units of a memory device. In particular, various embodiments provide for monitoring (e.g., tracking) of partial program/erase cycles for a memory unit (e.g., block) of a memory device, and performing an erasure of the memory unit based on the monitoring.

A system-on-chip includes a processor, a memory and a memory interface coupled to the processor and to the memory. The processor, in operation, generates memory access requests. The memory includes one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory. The memory interface, in operation, responds to receiving memory configuration information by storing logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of one or more logical memory banks. The memory interface, in operation, controls access to the memory by the processor based on the logical memory bank configuration information stored in the one or more configuration registers.

A method and terminal for OTA upgrading are described. In the method, a system image file of a terminal to be upgraded is saved in the form of data blocks. The method includes: acquiring and parsing an OTA upgrade package to obtain respective differential upgrade files for the system image file; reading data blocks corresponding to respective differential upgrade files in the system image file, and performing an upgrading operation on corresponding data blocks to upgrade the system image file. Split system image files are used rather than files in a file system as data for differential comparison. Thus metadata in the file system are also included in differential data packet. After the upgrading, the image in the terminal is fully consistent with the image in a production process and does not conflict with a system check mechanism.

In a first process, based on data of a FLASH status 0 area included in a first block of a flash ROM, a rewriting process including erasing, writing and verifying on blocks of the flash ROM storing a user program to be rewritten based on contents of a user program for rewriting is controlled. In a second process, the rewriting process is carried out without regard to the data of the FLASH status 0 area. In the first process, writing on the FLASH status 0 area is not carried out in the rewriting process on the first block of the flash ROM, but writing on the FLASH status 0 area is carried out based on the contents of the user program for rewriting after carrying out the rewriting process on a last block of the flash ROM.