A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured to, if the at least one memory string passes the erase-verify test, inhibit the at least one memory string for erase including ramping up, to an erase voltage, of a voltage applied to a gate of a SGD transistor of the at least one memory string and to perform a next erase-verify iteration in the erase operation for remaining memory strings of the plurality of memory strings other than the at least one memory string.

An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.

To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.