A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

A memory controller receives a command to program information to a memory storage array controlled by the memory controller. The memory controller determines a target memory state to store the information, and a target threshold voltage level corresponding to the target memory state. Based at least on the target memory state, the memory controller determines one or more program pulses for a pre-program cycle, including voltage levels for the one or more program pulses based at least on the target threshold voltage level. The memory controller selects a memory location in the memory storage array to program the information, and pre-programs the selected memory location by applying the one or more program pulses at respective voltage levels, the one or more program pulses applied without program verify operations. Following the pre-programming, the memory controller programs the information to the selected memory location.

A memory system includes non-volatile memory cells for storing multiple bit data and a controller configured to control to apply read voltages to the non-volatile memory cells at different threshold levels to read data written to the non-volatile memory cells. The non-volatile memory cells comprise different sub-groups. The controller stores first information indicating a first initial value for each of the different threshold level of the read voltages, second information that indicates whether data can be successfully read from each sub-group when the respective different threshold levels of the read voltages are set to the first initial values, and third information that indicates a second initial value for each different threshold level of the read voltages for at least one sub-group for which data reading was unsuccessful when a read voltage was set to the first initial value.

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.

A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled with the array of memory cells. The control logic is to perform operations including: causing first data to be programmed to a plurality of memory cells of the array of memory cells, the first data including a first erase distribution programmed below an erase threshold voltage (Vt) level and a first voltage distribution programmed relative to a first Vt level; and causing, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data including a second erase distribution programmed relative to the first Vt level and a second voltage distribution programmed relative to a second Vt level.

Embodiments provide a scheme for estimating an optimal read threshold voltage using a deep neural network (DNN) with a reduced number of processing. A controller includes a combined neural network, which receives first and second cumulative distribution function (CDF) values, each CDF value corresponding to a program voltage (PV) level associated with a read operation on the cells. The combined neural network generates first and second connection vectors based on the first and second CDF values and first weight values, and estimates an optimal read threshold voltage based on the first and second connection vectors and second weight values.

A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.

A memory device includes a memory array of memory cells. A page buffer is to apply, to a bit line, a first voltage or a second voltage that is higher than the first voltage during a program verify operation. Control logic operatively coupled with the page buffer is to perform operations including: causing a plurality of memory cells to be programmed with a first program pulse; measuring a threshold voltage for the memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the memory cells as having a faster quick charge loss than that of a second subset of the memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells.

A method includes determining, via status polling at a first interval, an indicator of an almost ready status of a set of memory cells of a memory device, based on the indicator of the almost ready status, determining the set of memory cells of the memory device is almost ready to complete execution of an operation on the set of memory cells of the memory device, and responsive to determining the set of memory cells of the memory device is almost ready to complete execution of the operation, performing status polling at a second interval.