A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured to, if the at least one memory string passes the erase-verify test, inhibit the at least one memory string for erase including ramping up, to an erase voltage, of a voltage applied to a gate of a SGD transistor of the at least one memory string and to perform a next erase-verify iteration in the erase operation for remaining memory strings of the plurality of memory strings other than the at least one memory string.

A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.

A method and solid-state storage device are disclosed for validating erasure status of data blocks on a solid-state drive. The method includes assigning each data block of a plurality of data blocks on the solid-state drive, a block identifier and an erasure status, the block identifier being system data, user data, or unmapped data, and the erasure status being erased or not erased.

A memory device includes a memory array of memory cells and control logic operatively coupled to the memory array. The control logic to perform memory erase operations including: performing a true erase sub-operation by causing multiple pulse steps to be applied sequentially to a group of memory cells of the memory array, wherein each sequential pulse step of the multiple pulse steps occurs during a pulse-step period and at a higher voltage compared to an immediately-preceding pulse-step; in response to detecting an erase suspend command during a pulse step, suspending the true erase sub-operation at a start of a subsequent pulse-step period after the pulse step; and resuming the true erase sub-operation at an end of the subsequent pulse-step period.

A memory device includes a common source line, a memory cell array, bit lines, and a conductive layer. The common source line is formed on a substrate. The memory cell array is formed on the common source line. The bit lines are connected to the memory cell array. The conductive layer is formed over the bit lines. In an erase operation, the memory device increases a voltage of the bit lines to an erase voltage through capacitive coupling by increasing a voltage applied to the conductive layer.

A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. For at least a subset of the unselected memory cells, the pass voltage that is applied is dependent upon the position of the selected memory cell in the group. As programming progresses from a memory cell at a first end of a NAND string toward a memory cell at a second end of the NAND string, for example, the pass voltage for at least a subset of the unselected memory cells that have already been subjected to programming may be increased. This technique may reduce the effects of an increased channel resistance that occurs as more memory cells are programmed.

A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.