Disclosed approaches for validating initialization vectors determining by a configuration control circuit whether or not an input initialization vector is within a range of valid initialization vectors. In response to determining that the initialization vector is within the range of valid initialization vectors, the configuration control circuit decrypts the ciphertext into plaintext using the input initialization vector and configures a memory circuit with the plaintext. In response to determining that the first initialization vector is outside the range of valid initialization vectors, the configuration control circuit signals that the first initialization vector is invalid.

A method for writing to a non-volatile electronic memory with data words and assigned pieces of index information. The non-volatile electronic memory is initially filled exclusively with empty data frames. The empty data frames are overwritable with multi-data frames and/or individual data frames. A multi-data frame includes a selectable number of sequentially stored data words, and a multi-data frame header. A frame-type marker, the number of data words, and a selectable start index are stored in the multi-data frame header so that each data word is assignable a unique index value from an index interval by incrementing or decrementing. An individual data frame includes one data word and an individual data frame header. A frame-type marker and a selectable index value for the one data word of the individual data frame are stored in the individual data frame header.

A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.

In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.

A memory device is provided. The memory device includes a bit cell having a first invertor connected between a first node and a second node and a second invertor connected between the first node and the second node. The first invertor and the second invertor are cross coupled at a first data node and a second data node. The memory device further includes a pull down circuit connected to the second node. The pull down circuit is operative to pull down a voltage of the second node below a ground voltage in response to an enable signal.

The present invention relates to a single-layer polysilicon nonvolatile memory cell, a group structure thereof and a memory including the same. The memory cell includes a selection transistor and a storage transistor, wherein the selection transistor is connected in series with the storage transistor; and the selection transistor and the storage transistor are arranged on a substrate in a mutually perpendicular manner. A memory cell group includes four memory cells, arranged in a center-symmetrical array of two rows×two columns. The memory comprises at least one memory cell group. The memory cell and the memory thereof are used as a one-time programming memory cell and memory, and have the advantages of small area, high programming efficiency and capability, and strong data retention capability.

The present invention relates to a single-layer polysilicon nonvolatile memory cell, a group structure thereof and a memory including the same. The memory cell includes a selection transistor and a storage transistor, wherein the selection transistor is connected in series with the storage transistor; and the selection transistor and the storage transistor are arranged on a substrate in a mutually perpendicular manner. A memory cell group includes four memory cells, arranged in a center-symmetrical array of two rows×two columns. The memory comprises at least one memory cell group. The memory cell and the memory thereof are used as a one-time programming memory cell and memory, and have the advantages of small area, high programming efficiency and capability, and strong data retention capability.

A one-time programmable (OTP) memory device includes an access transistor, a word line, a voltage line, a well, a first filling oxide layer, a first semiconductor layer, and a bit line. The access transistor includes a gate structure on a substrate, and first and second impurity regions at portions of the substrate adjacent to the gate structure. The word line is electrically connected to the gate structure. The voltage line is electrically connected to the first impurity region. The well is formed at an upper portion of the substrate, and is doped with impurities having a first conductivity type. The first filling oxide layer is formed on the well. The first semiconductor layer is formed on the first filling oxide layer, and is doped with impurities having the first conductivity type and electrically connected to the second impurity region. The bit line is electrically connected to the well.

The present invention relates to a dynamic random access memory and a programming method therefor with two stages. In a first stage, a capacitor of a memory cell of the dynamic random access memory is broken down, so that the dynamic random access memory becomes a one-time programmable memory. In a second stage, a resistance of the capacitor that is broken down is reduced, so that state data of the memory cell can be more easily interpreted.

In one example a semiconductor device has a data latch that includes first and second transmission gates and first and second inverters. The first inverter is connected between a first terminal of the first transmission gate and a first terminal of the second transmission gate. The second inverter is connected between a second terminal of the first transmission gate and a second terminal of the second transmission gate. The data latch is configured to store a datum received at the connection between the first transmission gate and the second inverter, and to store a datum received at the connection between the second transmission gate and the first inverter.