A shift register includes a pull-up control circuit, at least two output circuits, a pull-down control circuit, at least two pull-down circuits, and at least two output signal terminals. The pull-up control circuit, the at least two output circuits, and the pull-down control circuit are respectively coupled to the pull-up node; the pull-down control circuit, the at least two pull-down circuits, and the pull-up control circuit are respectively coupled to the pull-down node. Each of the at least two output circuits is coupled to a corresponding one of the at least two output signal terminals; each of the at least two pull-down circuits is coupled to a corresponding one of the at least two output signal terminals; and each of the at least two output signal terminals is coupled to a corresponding one of at least two gate lines.

A shift register circuit is disclosed that includes an initialization circuit, a first node control circuit, a second node control circuit, and an output circuit. The initialization circuit is configured to set a first node to an inactive potential in response to an initialization pulse from an initialization terminal being active. The initialization pulse is immediately prior to an input pulse applied to an input terminal.

A shift register circuit is disclosed that includes an initialization circuit, a first node control circuit, a second node control circuit, and an output circuit. The initialization circuit is configured to set a first node to an inactive potential in response to an initialization pulse from an initialization terminal being active. The initialization pulse is immediately prior to an input pulse applied to an input terminal.

A shift register includes a pull-up control circuit, at least two output circuits, a pull-down control circuit, at least two pull-down circuits, and at least two output signal terminals. The pull-up control circuit, the at least two output circuits, and the pull-down control circuit are respectively coupled to the pull-up node; the pull-down control circuit, the at least two pull-down circuits, and the pull-up control circuit are respectively coupled to the pull-down node. Each of the at least two output circuits is coupled to a corresponding one of the at least two output signal terminals; each of the at least two pull-down circuits is coupled to a corresponding one of the at least two output signal terminals; and each of the at least two output signal terminals is coupled to a corresponding one of at least two gate lines.

A display device may include a plurality of rows of pixels configured to display image data on a display and a first gate driver circuit. The first gate driver circuit may couple a first voltage source to a first node associated with a first gate of a first switch upon receipt of a start signal or a gate signal from another gate driver circuit and couple a first clock signal to a first gate line via the first switch after a first voltage of the first node exceeds a threshold. The threshold is associated with activating the first switch, such that the first gate line is configured to couple to a first row of the plurality of rows of pixels. The first gate driver circuit may then couple a second voltage source to the first node based on a second clock signal, such that the second voltage source discharges the first node.

Provided are an array substrate, a display panel and a display device, and the array substrate includes: at least one pressure sensor disposed in the non-display region; and the pressure sensor includes a first resistor, a second resistor, a third resistor and a fourth resistor; and a plurality of shift registers disposed in the non-display region, and the first resistor, the second resistor, the third resistor and the fourth resistor are disposed at least one of following positions: inside the shift register, between adjacent two of the plurality of shift registers, at a side of the plurality of shift registers close to the display region, and at a side of the plurality of shift registers away from the display region.

The present disclosure provides a scan driving circuit for driving an Nth-stage scanning line including: a pull-up control module for receiving a cascade signal of an upper stage and generating a scan level signal of the Nth-stage scanning line based on the cascade signal of the upper stage; a pull-up module for pulling down the scanning signal of the Nth-stage scanning line when the first clock signal is low according to the scan level signal and the first clock signal; the pull-up control module includes a first control unit and a second control unit, the control terminal of the second control unit inputs a second clock signal for controlling the scan level signal to become smaller when the second clock signal is at a high level. The present disclosure can prevent the waveform of the gate from appearing spikes, and thus the waveform of the gate is output normally.

A shift register unit, a shift register, a gate driving circuit and a display device are discloses. The shift register unit has an output node Out(n) of a current stage, a pull-up node PU and a pull-down node PD, and the shift register unit includes a first capacitor module C1, a pull-down module and a pull-down control module, and the pull-down control module is configured to output one of a high level signal and a low level signal to the pull-down node (PD) in accordance with a current operating phase.

The present disclosure relates to a driving method and a driving unit of GOA circuits. The driving unit includes a timing control chip and a GOA circuit including a plurality of cascaded GOA driving units. The timing control chip inputs first clock signals, second clock signals, and a constant-voltage potential to the GOA driving units at each of levels to drive the GOA driving units to output the scanning driving signals level-by-level, wherein scanning initial signals are further inputted to the GOA driving units at the first through the fourth level. The first clock signals and the second clock signals are two different clock signals selected from one clock signals set including eight high-frequency clock signals (CK.sub.1CK.sub.8), wherein CK.sub.m and CK.sub.m+4 are inverting signals. A period of each of the high-frequency clock signals is T, and a high-potential pulse width within the period (T) is T.sub.1 During a scanning driving process of each of frames, the high-potential pulse width of the high-frequency clock signals (CK.sub.m) is T.sub.1m, T.sub.1m<T.sub.1, m=1, 2, 3, and 4.

The present disclosure relates to a driving method and a driving unit of GOA circuits. The driving unit includes a timing control chip and a GOA circuit including a plurality of cascaded GOA driving units. The timing control chip inputs first clock signals, second clock signals, and a constant-voltage potential to the GOA driving units at each of levels to drive the GOA driving units to output the scanning driving signals level-by-level, wherein scanning initial signals are further inputted to the GOA driving units at the first through the fourth level. The first clock signals and the second clock signals are two different clock signals selected from one clock signals set including eight high-frequency clock signals (CK.sub.1CK.sub.8), wherein CK.sub.m and CK.sub.m+4 are inverting signals. A period of each of the high-frequency clock signals is T, and a high-potential pulse width within the period (T) is T.sub.1 During a scanning driving process of each of frames, the high-potential pulse width of the high-frequency clock signals (CK.sub.m) is T.sub.1m, T.sub.1m<T.sub.1, m=1, 2, 3, and 4.