To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10.sup.−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

It is an object to provide a semiconductor device which can supply a signal with sufficient amplitude to a scan line while power consumption is kept small. Further, it is an object to provide a semiconductor device which can suppress distortion of a signal supplied to the scan line and shorten a rising time and a falling time while power consumption is kept small A semiconductor device which includes a plurality of pixels each including a display element and at least one first transistor and a scan line driver circuit supplying a signal for selecting the plurality of pixels to a scan line. A light-transmitting conductive layer is used for a pixel electrode layer of the display element, a gate electrode layer of the first transistor, source and drain electrode layers of the first transistor, and the scan line. The scan line driver circuit includes a second transistor and a capacitor for holding a voltage between a gate electrode layer of the second transistor and a source electrode layer of the second transistor. The source electrode of the second transistor is connected to the scan line.

To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

The present system is directed to a modular apparatus that may be assembled and disassembled repeatedly without the use of tools. The modular system includes connectors that may be fixed to the underside of a plank and then engaged with leg portions. The connectors further include channels to accommodate retention members of additional attachments, such as covers, guards, signage, or racks that may be added onto the modular apparatus to increase its utility. The retention members mate with the connectors to connect and securely hold the attachment and can be removed from the connectors all without the need for tools.

A shift register includes stages each constituted by a unit circuit provided with a thin-film transistor (separation transistor) that separates a control node into an output-side first control node and an input-side second control node and a capacitor whose first end is connected to the second control node. The thin-film transistor (separation transistor) has a control terminal that is supplied with a high-level DC power supply voltage. Typically, the channel width of a thin-film transistor (first output control transistor) that controls output from a unit circuit is ten or more times greater than the channel width of the thin-film transistor (separation transistor).

A display device includes pixel circuit rows, selection lines connected to the pixel circuit rows, and a shift register including linked shift register units. The shift register units output sequential selection pulses to the selection lines. Each of the shift register units outputs the selection pulse to a corresponding selection line among the selection lines. Each of the shift register units includes thin film transistors of a first conductivity type that are connected in parallel, and that, during an ON state, connect the corresponding selection lines to a fixed potential wiring line for applying a non-selection level for the selection pulse. During each frame period, the thin film transistors are turned ON/OFF by clock signals in different phases. The duty cycle of the ON period of each of the thin film transistors during each said frame period is 12.5% or less.

A shift register unit, drive method thereof, gate drive device and display device. The shift register unit includes: an input subcircuit; a reset subcircuit; an output subcircuit configured to provide a clock signal at a clock signal end to a current stage shift register unit output end in response to a voltage signal at the pull-up node and a control signal having a first voltage level, and to disable an output at the current stage output end in response to the control signal having a second voltage level; a pull down control subcircuit configured to provide a second voltage signal having a low voltage level to a pull-down node in response to the voltage signal at the pull-up node, and to provide the voltage signal having a high voltage level to the pull-down node in response to the voltage signal having a high voltage level; and a pull down subcircuit

A display includes a substrate having a driver circuit with hybrid devices. The driver circuit includes first to fourth transistors. The first transistor includes a first control end connected to a clock signal, a first end connected to a high voltage, and a second end connected to a first node. The second transistor comprises metal oxide semiconductor, and includes a second control end connected to an input signal, a third end connected to a second node, and a fourth end connected to the first node. The third transistor comprises polysilicon semiconductor, and includes a third control end connected to the first node, and a fifth end connected to the high voltage, and a sixth end connected to an output voltage. The fourth transistor includes a fourth control end connected to the input signal, a seventh end connected to the third node, and an eighth end connected to the output voltage.

A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

A display may have an array of pixels to display images. Gate line driver circuitry may have stages that supply gate line signals. A gate line may be located in each row of the pixels. Each stage may have an output block that produces a respective one of the gate line signals and may have a carry block that separately produces a carry signal that is provided to a later stage in the gate line driver circuitry. A memory may be provided in at least some of the stages to store signals produced by the output blocks during intraframe pausing operations. At the end of an intraframe pause, the stored signals may be used in restarting production of the gate line signals by output blocks in the gate line driver stages. Circuitry may be used to separately reset the output block and suppress carry signal production by the carry block.