This application discloses a shift register, a gate drive circuit and a display device. The signal of the input signal terminal is provided to the pull-up node by the input circuit under the control of the input signal terminal; and the signal of the second reference signal terminal is provided to the output signal terminal by the output circuit under the control of the clock signal terminal and the signal of the pull-up node. The signal of the first reference signal terminal is provided to the pull-up node by the reset circuit under the control of the input signal terminal and the clock signal terminal. The pull-down control circuit resets the output signal terminal according to the signal of the first reference signal terminal.

A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

A marching memory includes an alternating periodic array of odd-numbered columns (U.sub.1, U.sub.2, . . . , U.sub.n1, U.sub.n) and even-numbered columns (Ur.sub.1, Ur.sub.2, . . . , Ur.sub.n1, Ur.sub.n). Each of the odd-numbered columns (U.sub.1, U.sub.2, . . . , U.sub.n1, U.sub.n) has a sequence of front-stage cells aligned along a column direction so as to store a set of moving information of byte size or word size. And each of the even-numbered columns (Ur.sub.1, Ur.sub.2, . . . , Ur.sub.n1, Ur.sub.n) has a sequence of rear-stage cells aligned along a column direction so as to store the set of moving information, so that the set of moving information can be transferred synchronously, step by step, along a direction orthogonal to the column direction.

A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

The present disclosure relates to a shiftable memory comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected, thereby forming chains of memory cells; at least one first serial output data port; output data logic for connecting an output of any of the chains of memory cells to the first serial output data port, or at least one first parallel output data port and at least one read shift register configured for serially collecting serial output data from the output of any of the chains of memory cells; and/or at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any of the chains of memory cells, or at least one parallel input data port and at least one write shift register for serially shifting input data to the input of any of the chains of memory cells; and a controller configured to control the shifting of the data in the chains of memory cells, the controller further configured to control the output data logic and/or the input data logic. The disclosure further relates to a method for operating the shiftable memory.

A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

A scan driving circuit includes a plurality of stages, each having a shift register and a scan signal output unit. The shift register has a first node to receive a first driving voltage according to a control signal and a second node to receive the first driving voltage according to a reset signal. The scan signal output unit outputs scan signals to respective scan lines. The scan signal output unit has a plurality of clock switches controlled according to a voltage of the first node and a plurality of switches controlled according to a voltage of the second node. The clock switches sequentially output clock signals to respective third nodes, which are connected to respective scan lines. The switches output a second driving voltage to the third nodes.

A precharging circuit, a scanning driving circuit, an array substrate, and a display device are provided. The precharging circuit includes an input end, an output end, and further includes a switching unit, first pull-up unit, and second pull-up unit. The switching unit has first end connected to first node; second end connected to the input end, and third end connected to second node, and is used for conducting the second end and the third end when first end is at high level; first pull-up unit has first end connected to the output end and second end connected to first node, and is used for pulling up potential of second end when first end is at high level; second pull-up unit has first end connected to second node and second end connected to output end, is used for pulling up potential of second end when first end is at high level.

A shift register device including a plurality of shift registers is provided. The shift registers are coupled to each other in series, where an N.sup.th stage shift register includes a voltage setting circuit, at least two control signal generators, at least two backup control signal generators and an output stage circuit. The at least two control signal generators are coupled to a first control terminal and a second control terminal, and the at least two backup control signal generators respectively receive at least two backup bias voltages, and respectively generate the first control voltage and the second control voltage according to the at least two backup bias voltages.

There are presented a shift register and a driving method thereof, a gate driving circuit and a display apparatus. The shift register includes a first feedback module and a pull-down module, wherein the first feedback module comprises at least two feedback units, control terminals of respective feedback units are connected to different control points respectively, each feedback unit has an input terminal connected to a first level input terminal and an output terminal connected to a first node, the first node is connected to a control terminal of the pull-down module, and the pull-down module has an input terminal connected to the first level input terminal and an output terminal connected to a signal output terminal of the shift register. The shift register is used to enhance noise resistance capability of the shift register.