A signal processing method includes the following operations: receiving an input signal and analyzing the input signal to generate a plurality of bit codes by a signal receiving circuit; temporarily storing a first part of the plurality of bit codes according to a time sequence by a shift register and starting a decoder when the shift register is full; and performing a boundary calibration according to the first part of the plurality of bit codes by the decoder when the first part of the plurality of bit codes meets a decoding table rule and a boundary detection rule.

A pseudo-random sequence generator for use within a universal lidar system and its corresponding method of operation. The pseudo-random sequence generator uses synchronized shift registers that are in series Binary adders are provided. The signal output of each of the shift registers is tapped and directed to the binary adders. High-speed switches are provided between the shift registers and the binary adders. The switches are programmed to connect only two of the shift registers to the binary adders for each of the pseudo-random patterns being generated. The binary adders generate an output signal that is received by the first shift register. The signal propagates through all the shift registers to the last shift register. The last shift register outputs a pseudo-random sequence.

A register management system is coupled to a register. The register management system receives an address and functional data for a write operation to be performed on the register. The functional data includes write bits and mask bits associated with the write bits. One or more mask bits having a first logic state indicate that associated one or more write bits are to be written to the register, respectively. Based on the address, the register management system selects a first half of the register or a second half of the register to perform the write operation. Further, the register management system writes the one or more write bits associated with the one or more mask bits having the first logic state to one or more storage elements of the first half of the register or the second half of the register, respectively.

A network device includes a linear feedback shift register circuit and a value updating circuit. The linear feedback shift register circuit is configured to perform an auto crossover mechanism according to at least one clock signal and a plurality of first bits, in order to control at least one port of a first interface circuit to connect with a second interface circuit. The value updating circuit is configured to perform at least one of a plurality of operations according to exclusive information. The plurality of operations includes: generating a plurality of initial values, in which the value updating circuit is configured to utilize the plurality of initial values to update at least one partial bits of the plurality of first bits; or setting a period of the at least one clock signal, in which the exclusive information includes operational information or production information of the network device.

Shift register includes signal writing circuit, voltage control circuit and output circuit. The signal writing circuit is configured to write inverted signal of input signal provided by signal input terminal into second node responsive to control of second clock signal provided by second clock signal terminal. The voltage control circuit is configured to write first operating voltage into first node and write second clock signal into third node in voltage control circuit in response to control of voltage at first node, write second operating voltage into third node in response to control of second clock signal and write first clock signal provided by first clock signal terminal into first node in response to control of voltage at third node and first clock signal. The output circuit is configured to write second or first operating voltage into signal output terminal in response to control of voltage at first or second node.

A convolutional computation device includes: a two-dimensional circulation shift register unit that has a plurality of storage elements, cyclically shifts the data among the plurality of storage elements, provides at least one input window in a predetermined area, and selects the data stored in one of the storage elements disposed in the input window as input data; and at least one multiplier-accumulator that generates output data by performing a multiply-accumulate operation on the input data input from the two-dimensional circulation shift register unit and weight data for providing a predetermined filter.

Shift register includes signal writing circuit, voltage control circuit and output circuit. The signal writing circuit is configured to write inverted signal of input signal provided by signal input terminal into second node responsive to control of second clock signal provided by second clock signal terminal. The voltage control circuit is configured to write first operating voltage into first node and write second clock signal into third node in voltage control circuit in response to control of voltage at first node, write second operating voltage into third node in response to control of second clock signal and write first clock signal provided by first clock signal terminal into first node in response to control of voltage at third node and first clock signal. The output circuit is configured to write second or first operating voltage into signal output terminal in response to control of voltage at first or second node.

An object of the present invention is to suppress deterioration in the thin film transistor. A plurality of pulse output circuits each include first to eleventh thin film transistors is formed. The pulse output circuit is operated on the basis of a plurality of clock signals which control each transistor, the previous stage signal input from a pulse output circuit in the previous stage, the next stage signal input from a pulse output circuit in the next stage, and a reset signal. In addition, a microcrystalline semiconductor is used for a semiconductor layer serving as a channel region of each transistor. Therefore, degradation of characteristics of the transistor can be suppressed.

A shift register unit and a driving method thereof, a gate driving circuit and a display apparatus are provided. The shift register unit comprises: an input circuit, a transmission circuit and an output control circuit; wherein the transmission circuit is coupled to a first node, a second node, a clock signal terminal and a first power source terminal, respectively, and is configured to control an electric potential of the second node under the control of the first node, the clock signal terminal and the first power source terminal, and the output control circuit is configured to control an electric potential of the output signal terminal under the control of the second node. The electric potential of the output signal from the output signal terminal in the shift register unit can be controlled by adopting one clock signal terminal, which effectively reduces the power consumption of the shift register unit.

A shift register unit and a driving method thereof, a gate driving circuit and a display apparatus are provided. The shift register unit comprises: an input circuit, a transmission circuit and an output control circuit; wherein the transmission circuit is coupled to a first node, a second node, a clock signal terminal and a first power source terminal, respectively, and is configured to control an electric potential of the second node under the control of the first node, the clock signal terminal and the first power source terminal, and the output control circuit is configured to control an electric potential of the output signal terminal under the control of the second node. The electric potential of the output signal from the output signal terminal in the shift register unit can be controlled by adopting one clock signal terminal, which effectively reduces the power consumption of the shift register unit.