A phase change (PCM) memory device that includes a PCM and a resistance-capacitance (RC) circuit. The PCM has one or more PCM properties, each PCM property has a plurality of PCM property states. As the PCM property states of a given property are Set or Reset, the PCM property states each produce an incremental change to a property level of the respective/associated PCM property, e.g., PCM conductance. The incremental changes to property level of the PCM memory device are in response to application of one or more of a pulse number of voltage pulses. The RC circuit produces a configuring current that flows through the PCM in response to one or more of the voltage pulses. The configuring current modifies one or more of the incremental changes to one or more of the property levels so that the property level changes lineally with respect to the pulse number. The PCM memory device has use in a synapse connector, e.g., in a memory array. The memory array can be used to store and/or read memory values associated with one or more of the property levels. The memory values can be used as weighting values in a neuromorphic computing application/system, like a neural network.

A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.

Embodiments provide a selector device for selecting a memory cell. The selector device includes a first electrode; a second electrode; and a switching layer sandwiched between the first electrode and the second electrode. The switching layer includes at least one metal rich layer and at least one chalcogenide rich layer. The metal rich layer includes at least one of a metal or a metal compound, wherein metal content of the metal rich layer is greater than 50 at. %. The chalcogenide content of the chalcogenide rich layer is greater than 50 at. %.

A control method to operate a memory device, a control method to operate a memory system and a control system are provided. The control method includes providing a first voltage to a memory device for accessing a memory element of the memory device; obtaining an aging information of the memory device; and providing a second voltage to the memory device according to the aging information, wherein the first voltage and the second voltage are reverse biased voltages.

Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

Methods, systems, and devices for multi-component cell architectures for a memory device are described. A memory device may include self-selecting memory cells that include multiple self-selecting memory components (e.g., multiple layers or other segments of a self-selecting memory material, separated by electrodes). The multiple self-selecting memory components may be configured to collectively store one logic state based on the polarity of a programming pulse applied to the memory cell. The multiple memory component layers may be collectively (concurrently) programmed and read. The multiple self-selecting memory components may increase the size of a read window of the memory cell when compared to a memory cell with a single self-selecting memory component. The read window for the memory cell may correspond to the sum of the read windows of each self-selecting memory component.

A semiconductor device may include first row lines each extending in a first direction, column lines each extending in a second direction crossing the first direction, second row lines each extending in the first direction, a plurality of first memory cells respectively coupled between the first row lines and the column lines, each of the plurality of first memory cells including a first variable resistance layer and a first dielectric layer positioned between the first variable resistance layer and a corresponding one of the first row lines, and a plurality of second memory cells respectively coupled between the second row lines and the column lines, each of the plurality of second memory cells including a second variable resistance layer and a second dielectric layer positioned between the second variable resistance layer and a corresponding one of the second row lines.

A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

A nonvolatile memory device comprises: resistive memory cells each of which takes either a variable state or an initial state, the resistive memory cells including at least one resistive memory cell in the initial state; and a read circuit that comprising a resistance detection circuit that obtains resistance value information of the at least one resistive memory cell, and a data generation circuit that generates digital data corresponding to the resistance value information. The resistance detection circuit applies a second read voltage to the at least one resistive memory cell to obtain the resistance value information. The second read voltage is larger than a first read voltage and smaller than a voltage of a forming pulse that is an electrical stress for changing from the initial state to the variable state. The first read voltage is for reading a resistive memory cell in the variable state.