The present technology relates to an electronic device. A memory device according to the present technology includes a plurality of memory cells connected to a word line, an operation controller configured to apply a first or a second read voltage to the word line and to obtain data that is stored in the plurality of memory cells through bit lines that are respectively connected to the plurality of memory cells, and a read voltage controller configured to control the operation controller to read the data that is stored in the plurality of memory cells by using the second read voltage, and to read the data that is stored in the plurality of memory cells by using the first read voltage according to the number of off cells that are counted based on the data that is read by using the second read voltage, in response to a read command.

Disclosed are methods, systems and devices for generation of a read signal to be applied across a load for use in detecting a current impedance state of the load. In one implementation, a voltage and current of a generated read signal may be controlled so as to maintain a current impedance state of the load.

Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.

Circuit and method for controlling a resistive memory formed by resistive memory cells each provided with a resistive memory element associated in series with a selector, each cell implementing a coding referred to as “multi-level” coding and being programmed in a given programming state among k (with k>2) possible programming states, wherein during a read operation, a sequence of different read voltages are applied to the given cell, and at each applied read voltage it is detected whether the read current passing through said given cell consecutively to the application of said read voltage corresponds to a leakage current level of the selector when this selector is in an off state or to a current level when the selector is in an on state.

A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage at a first time duration to the memory array based on the read request. The control circuit is additionally configured to count a number of the plurality of memory cells that have switched to an active read state based on the first voltage and to derive a second time duration. The control circuit is further configured to apply a second voltage at the second duration to the memory array. The control circuit is also configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.

A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage to the memory array based on the read request. The control circuit is additionally configured to count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage and to apply a second voltage to the memory array based on the total number. The control circuit is further configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.

In a method for accessing memory cells, a first read operation is performed on a first memory cell to read a first data value from the first memory cell. During the first read operation, a first variable current source provides a first assessment current having a first current level to a first bitline coupled to the first memory cell. A second read operation is performed on the first memory cell to read a second data value from the first memory cell. During the second read operation, the first variable current source manipulates the first current level to provide a second current level to the first bitline. A difference between the first current level and the second current level is based on whether the first data value that was read during the first read operation was a first data state or a second data state.