Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.

A method of testing a semiconductor package including a plurality of semiconductor chips includes sensing electrical signals respectively output from a plurality of semiconductor chip groups each representing a combination of at least two semiconductor chips among the plurality of semiconductor chips, obtaining amplitudes of electrical signals respectively output from the plurality of semiconductor chips based on the plurality of sensed electrical signals, and outputting a test result for the semiconductor package by using the plurality of obtained electrical signals.

The present disclosure provides a semiconductor testing apparatus with a connected unit, which is applied to a wafer probing testing or a final testing. The semiconductor testing apparatus comprises a semiconductor testing printed circuit board, a functional module and the connected unit. First contact points are disposed on a first surface of the semiconductor testing printed circuit board, and electrically connected to the functional module. Second contact points are disposed on a second surface of the semiconductor testing printed circuit board, and electrically connected to a functional controller. The first contact points and the second contact points have independent and non-interfering working time domains. Therefore, the present disclosure can utilize the area of the semiconductor testing printed circuit board, and can independently perform functional testing of a wafer or packaged integrated circuit devices using multiple time domains, in a multi-time domain, synchronous or asynchronous manner.

A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

A method and a device for memory testing, and a computer-readable storage medium are provided. In the method, an instruction signal is sent to the memory, the instruction signal comprising a randomly generated write instruction or read instruction; a valid Column Address Strobe (CAS) instruction for ensuring running of the instruction signal is randomly inserted before the instruction signal by detecting a specific type of the instruction signal, and at least one of a redundant CAS instruction or invalid command irrelevant to the instruction signal is randomly generated and inserted; and the memory is enabled to run the instruction signal, the inserted valid CAS instruction, and the at least one of the redundant CAS instruction or the invalid command, and the running of the memory is tested.

A test device includes a test plate and an adapter box. The rest plate includes a test port, and a first positioning portion disposed on the test plate. The adapter box includes a box body configured to detachably mount Solid State Drives to be tested, and a second positioning portion disposed on the box body and configured to cooperate with the first positioning portion to cause the Solid State Drives to be tested to form a communication connection with the test port.

A probe device includes a first receiving terminal configured to receive a multi-level signal having M levels, where M is a natural number greater than 2; a second receiving terminal configured to receive a reference signal; a receiving buffer including a first input terminal connected to the first receiving terminal, a second input terminal connected to the second receiving terminal, and an output terminal configured to output the multi-level signal based on signals received from the first and second input terminals; and a resistor circuit comprising a plurality of resistors connected to the first and second receiving terminals and determining a magnitude of a termination resistance of the first and second receiving terminals.

Noise injection systems and methods for conducting power noise susceptibility tests on memory systems, including solid state drives. A noise injection system comprises a power selector to deliver a voltage at a first or second level according to a frequency level indicated by a frequency select signal; a noise signal relay to receive a frequency noise signal and to deliver a low or high frequency noise component of the frequency noise signal according to the frequency level of the frequency select signal; and an amplification assembly, responsive to the frequency select signal and which receives the first or second level voltage based on the frequency level of the frequency select signal, receives and amplifies the high frequency noise component when the frequency select signal indicates a high frequency level, and receives and amplifies the low frequency noise component when the frequency select signal indicates a low frequency level.

A test and measurement instrument includes a first data channel including a first data converter operating at a first rate, and a second data channel including a second data converter operating at a second rate that is different than the first rate. Rate controls may include a clock generation circuit. The clock generation circuit includes an intermediate frequency generator structured to generate an intermediate frequency clock from a first clock reference signal, a first frequency clock generator structured to generate a first frequency clock directly from the intermediate frequency clock, and a second frequency clock generator structured to generate a second frequency clock directly from the intermediate frequency clock. The first frequency clock may be used to control the rate of the first data channel, and the second frequency clock may be used to control the rate of the second data channel. Methods are also described.

A power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is triggered in response to an expected load change. An Automated test equipment for testing a device under test comprises a power supply, which is configured to supply the device under test. The automated test equipment comprises a pattern generator configured to provide one or more stimulus signals for the device under test. The power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is activated in synchronism with one or more of the stimulus signals and/or in response to one or more response data signals from the device under test. Corresponding methods and a computer program are also described.