A test and measurement instrument includes a first data channel including a first data converter operating at a first rate, and a second data channel including a second data converter operating at a second rate that is different than the first rate. Rate controls may include a clock generation circuit. The clock generation circuit includes an intermediate frequency generator structured to generate an intermediate frequency clock from a first clock reference signal, a first frequency clock generator structured to generate a first frequency clock directly from the intermediate frequency clock, and a second frequency clock generator structured to generate a second frequency clock directly from the intermediate frequency clock. The first frequency clock may be used to control the rate of the first data channel, and the second frequency clock may be used to control the rate of the second data channel. Methods are also described.

The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.

A redundancy analysis method of replacing a faulty part of a memory with at least one spare according to the present embodiment includes: acquiring fault information of the memory; and redundancy-allocating the fault with combinations of the spares to correspond to combination codes corresponding to the combinations of the spares, in which, the redundancy-allocating with the combination of the spare areas includes performing parallel processing on each combination of the spares.

A system and method for defect localization in embedded memory are provided. Embodiments include a system including automated testing equipment (ATE) interfaced with a wafer probe including a diagnostic laser for stimulating a DUT with the diagnostic laser at a ROI. The ATE is configured to simultaneously perform a test run at a test location of the DUT with a test pattern during stimulation of the DUT. Failing compare vectors of a reference failure log of a defective device are stored. A first profile module is configured to generate a first 3D profile from each pixel of a reference image of the defective device. A second profile module is configured to generate a second 3D profile from each pixel of the ROI of the DUT. A cross-correlation module is configured to execute a pixel-by-pixel cross-correlation from the first and second 3D profiles and generate an intensity map corresponding to a level of correlation between the DUT and defective device.

A redundancy analysis method of replacing a faulty part of a memory with at least one spare according to the present embodiment includes: acquiring fault information of the memory; and redundancy-allocating the fault with combinations of the spares to correspond to combination codes corresponding to the combinations of the spares, in which, the redundancy-allocating with the combination of the spare areas includes performing parallel processing on each combination of the spares.

A repair system and a repair method for a semiconductor structure, a storage medium, and an electronic device are provided. The semiconductor structure includes a main memory area and a redundant memory area. The repair system of the present disclosure includes a test circuit, a control circuit, and a repair circuit. The test circuit is configured to perform defect detection on the main memory area to determine a failed cell of the main memory area and position information of the failed cell. The control circuit is connected to the test circuit, and is configured to store the position information of the failed cell and generate a repair signal according to the position information. The repair circuit is connected to the control circuit, and is configured to receive the repair signal and perform a repair operation on the failed cell through the redundant memory area.

A test system for a memory card includes a first circuit board. One side of the first circuit board is provided with a plurality of contact groups spaced apart from each other along a row direction. Another side of the first circuit board is provided with slots disposed along the row direction. The test system further includes a second circuit board. The second circuit board is provided with a test circuit, and is inserted into the slot along a direction perpendicular to the first circuit board. The second circuit board provides a test signal to the contact groups.

A method of obtaining a physical property of a test sample, comprising a conductive or semi-conductive material (line/area/volume), by performing electric measurements using a multi-terminal microprobe. Periodic Joule heating within the test sample is induced by passing an ac current across a first pair of probe terminals electrically connected to the test sample, measuring the voltage at one and three times the power supply frequency of the current-conducting terminals across a second pair of probe terminals electrically connected to the test sample, and calculating the temperature-modulated property(ies) of the test sample as a function of the voltage measurements at said frequencies. A value proportional to the Temperature Coefficient of Resistivity (TCR), an Electrical Critical Dimension (ECD), or the true resistivity of the test sample at the ambient experimental temperature by subtracting a measurable TCR offset from the apparent (heating-affected) resistivity of the test sample can be determined.

An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

A reliability evaluation apparatus according to the present embodiment is provided with a housing and a board insertable into the housing. A plurality of sockets are provided on the board. Semiconductor devices are respectively attachable to socket. The plurality of sockets have electrodes electrically connectable to terminals of the semiconductor devices. A heater is provided inside the housing. A controller is connected to the plurality of sockets and to the heater. The controller controls a voltage to be applied to the terminal of the semiconductor device and controls an output of the heater. A plurality of electromagnets are arranged inside the housing so as to be positioned above or below the plurality of sockets when the board is inserted into the housing.