Patent classifications
G11C2207/102
Selective compression circuitry in a memory device
Methods and systems for selectively compressing data lines of a memory device in selective compression circuitry. The selective compression circuitry receives multiple data lines and compression circuitry that selectively compresses inputs. The selective compression circuitry also includes control circuitry to receive data over via the data lines. The control circuitry, when in a compressed mode, transmits data from each of the data lines to the compression circuitry. Alternatively, in an uncompressed mode, the control circuitry transmits data from a first subset of the data lines to the compression circuitry while blocking data from a second subset of the data lines from being transmitted to the compression circuitry.
Reducing data using a plurality of compression operations in a virtual tape library
Embodiments are provided for reducing data using a plurality of compression operations in a computing storage environment. A speed of data writing to a virtual tape device and an availability of one or more processor devices for the virtual tape device may be monitored. One or more requests may be received for writing data to the virtual tape device. Data to be written to the virtual tape device, corresponding to a selected number of the one or more requests for writing the data, may be compressed according to both the speed of data writing to the virtual tape device and the availability of one or more processor devices for the virtual tape device. The compressed data may be stored in the virtual tape device in record units. Non-compressed data may be compressed in the virtual tape device at a subsequent period of time (e.g., future time period).
STORAGE DEVICE AND NON-VOLATILE MEMORY DEVICE
To determine whether or not to data is compressed at a timing when a non-volatile memory device receives the data from a host apparatus. A storage controller transmits a specified logical address range, an update frequency level of the specified logical address range, and specified data to a device controller. On the basis of the update frequency level of the specified logical address range, the device controller determines whether the specified data is compressed or not. When determination is made that the specified data is compressed, the device controller compresses the specified data to generate compressed data, and writes the compressed data into a non-volatile memory. When determination is made that the specified data is not compressed, the device controller writes the specified data into the non-volatile memory.
IN-MEMORY COMPUTATIONAL DEVICE WITH BIT LINE PROCESSORS
A computing device includes bit line processors, multiplexers and a decoder. Each bit line processor includes a bit line of memory cells and each cell stores one bit of a data word. A column of bit line processors stores the bits of the data word. Each multiplexer connects a bit line processor in a first row of bit line processors to a bit line processor in a second row of bit line processors. The decoder activates at least two word lines of the bit line processor of the first row and a word line in the bit line processor in the second row and enables a bit line voltage associated with a result of a logical operation performed by the bit line processor in the first row to be written into the cell in the bit line processor in the second row.
Controlling firmware storage density based on temperature detection
A data storage device stores data in non-volatile memory. In one approach, a method includes: storing software in a compressed format in a first mode (e.g., an SLC mode) in a non-volatile memory; exposing, while the software is stored in the first mode, the non-volatile memory to a temperature greater than a predetermined threshold; determining that the temperature of the non-volatile memory has fallen below the predetermined threshold; and in response to determining that the temperature of the non-volatile memory has fallen below the predetermined threshold: decompressing the stored software, and storing the decompressed software in a second mode (e.g., TLC mode) in the non-volatile memory. The second mode has a storage density higher than the first mode.
Storage device accelerator providing aggregation of divided plaintext data
The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.
MEMORY DEVICE AND MEMORY SYSTEM
A memory device includes: a plurality of memory cells; soft read logic configured to generate soft data by reading data from the plurality of memory cells in response to a soft read command from a controller, the soft data including at least a major symbol and at least a minor symbol; a compressor configured to generate compressed data by: encoding, into a code alphabet having a second length, a major source alphabet including repetitions of the major symbol by a first length among a plurality of source alphabets included in the soft data, and encoding, into a code alphabet having a longer length than the second length, a minor source alphabet including repetitions of the major symbol by a shorter length than the first length and ending with one minor symbol; and an interface configured to provide the compressed data to the controller.
Soft Data Compression For Non-Volatile Memory
An encoder of a storage medium receives, at a plurality of latches respectively associated with a plurality of memory cells, soft data corresponding to data subject to a read operation specified by the a storage controller, compresses the soft data, and stores the compressed soft data in a buffer before transmitting the compressed soft data to the storage controller. Upon the buffer being full, the encoder writes uncompressed soft data back to at least a subset of the plurality of latches, and upon completion of the writing of the uncompressed soft data, the encoder resumes compressing and storing of soft data in the buffer, and transmits the compressed soft data to the storage controller.
Apparatuses and methods for operations using compressed and decompressed data
The present disclosure includes apparatuses and methods for operations using compressed and decompressed data. An example method includes receiving compressed data to a processing in memory (PIM) device and decompressing the compressed data on the PIM device.
CONTROLLING FIRMWARE STORAGE DENSITY BASED ON TEMPERATURE DETECTION
A data storage device stores data in non-volatile memory. In one approach, a method includes: storing software in a compressed format in a first mode (e.g., an SLC mode) in a non-volatile memory; exposing, while the software is stored in the first mode, the non-volatile memory to a temperature greater than a predetermined threshold; determining that the temperature of the non-volatile memory has fallen below the predetermined threshold; and in response to determining that the temperature of the non-volatile memory has fallen below the predetermined threshold: decompressing the stored software, and storing the decompressed software in a second mode (e.g., TLC mode) in the non-volatile memory. The second mode has a storage density higher than the first mode.