A memory device includes a page made up of plural memory cells arranged in a column on a substrate. A page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line. The bit line is connected to a sense amplifier circuit via a switch circuit. At least one of word lines is selected and a refresh operation is performed to return the voltage of the channel semiconductor layer of the selected word line to the first data retention voltage by controlling voltages applied to the selected word line, the drive control line, the source line, and the bit line and thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer of the memory cell in which the voltage of the channel semiconductor layer is set to the first data retention voltage using the page write operation. The refresh operation is performed, with the switch circuit kept in a nonconducting state, concurrently with a page read operation of reading page data of a first memory cell group belonging to a first page into the sense amplifier circuit.

A P layer 2 having a band shape is on an insulating substrate 1. An N.sup.+ layer 3a connected to a first source line SL1 and an N.sup.+ layer 3b connected to a first bit line are on respective sides of the P layer 2 in a first direction parallel to the insulating substrate. A first gate insulating layer 4a surrounds a portion of the P layer 2 connected to the N.sup.+ layer 3a, and a second gate insulating layer 4b surrounds the P layer 2 connected to the N.sup.+ layer 3b. A first gate conductor layer 5a connected to a first plate line and a second gate conductor layer 5b connected to a second plate line are isolated from each other and cover two respective side surfaces of the first gate insulating layer 4a in a second direction perpendicular to the first direction. A third gate conductor layer 5c connected to a first word line surrounds the second gate insulating layer 4b. These components constitute a dynamic flash memory.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

A memory integrated circuit is provided. The memory integrated circuit includes a first memory array, a second memory array and a driving circuit. The first and second memory arrays are laterally spaced apart, and respectively include: memory cells, each including an access transistor and a storage capacitor coupled to the access transistor; bit lines, respectively coupled to a row of the memory cells; and word lines, respectively coupled to a column of the memory cells. The driving circuit is disposed below the first and second memory arrays, and includes sense amplifiers. Each of the bit lines in the first memory array and one of the bit lines in the second memory array are routed to input lines of one of the sense amplifiers.

A memory device includes pages containing memory cells arranged in an array on a substrate. In each memory cell, a voltage applied to a first gate conductor layer, second gate conductor layer, third gate conductor layer, first impurity layer, and second impurity layer is controlled to form a hole group by impact ionization inside a channel semiconductor layer, and a page write operation of holding the hole group and a page erase operation of removing the hole group are performed. The first impurity layer is connected to a source line, the second impurity layer to a bit line, the first gate conductor layer to a first plate line, the second gate conductor layer to a second plate line, and the third gate conductor layer to a word line. A page erase operation is performed without inputting a positive or negative bias pulse to the bit line and the source line.

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

A first dynamic flash memory cell formed on a first Si pillar 25a including an N.sup.+ layer 21a, a P layer 22a, and an N.sup.+ layer 21b, and a second dynamic flash memory cell formed on a second Si pillar 25b including a P layer 22b and an N.sup.+ layer 21c, the first dynamic flash memory cell and the second dynamic flash memory cell sharing the N.sup.+ layer 21b that is connected to a first bit line BL1, are stacked on top of one another on a P-layer substrate 20 to form a dynamic flash memory. In plan view, a first plate line PL1, a first word line WL1, a second word line WL2, and a second plate line PL2 extend in the same direction and are formed to be perpendicular to a direction in which the first bit line BL1 extends.

The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.