The present disclosure provides a content addressable memory (CAM) for repairing firmware of multi-plane read operations in a flash memory device. The CAM comprises a set of CAM registers configured to store a mapping table. The mapping table comprises a plurality of old addresses, each old address corresponding to a new address. The CAM also comprises N comparators coupling to the set of CAM registers, and configured to compare the old addresses with N input signals for performing the multi-plane read operations on N memory planes, wherein N is an integer greater than 1. The CAM further comprises N multiplexers coupling to the N comparators respectively and to the set of CAM registers, and configured to generate N output signals for the multi-plane read operations. At least one of the N output signals comprises the new address according to the mapping table and a comparison output by the comparators.

An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. Each non-volatile memory cell is configured to store a plurality of bits of a plurality of logical pages including at least a first bit of a first logical page, a second bit of a second logical page and a third bit of a third logical page. The control circuits are configured to select a subset of the plurality of logical pages for reading, perform pre-read steps, and read a first and at least a second selected logical page of the subset without performing pre-read steps between reading the first and second selected logical pages.

A memory device comprising multiple memory planes is disclosed. The memory device further comprises a first pump set coupled with the multiple memory planes, and configured to supply a first output voltage to multiple linear regulators during a steady phase, and a second pump set coupled with the multiple memory planes, and configured to supply a second output voltage to the multiple linear regulators during a ramping phase. The multiple linear regulators can includes a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines of the plurality of memory planes, and a second linear regulator set configured to regulate the first output voltage or the second output voltage to generate a second voltage bias for a second group of word lines of the plurality of memory planes.

According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to sample a flash memory cell that belongs to a die, by attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples; defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell; and determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample. The processor may belong to the sampling circuit or may not belong to the sampling circuit.

The present technology includes a memory device which includes a plurality of planes in which data is stored, a peripheral circuit configured to perform operations on the plurality of planes, micro-control circuits configured to control the peripheral circuit so that the operations on the plurality of planes are independently performed, and a memory manager including a control memory in which different control codes for controlling the peripheral circuit are stored, and configured to output the control codes to the micro-control circuits, wherein the memory manager is configured to sequentially output a selected control code among the control codes to the micro-control circuits respectively corresponding to the planes.

Control logic in a memory device initiates a first loop of a program operation, the first loop comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of the memory array are programmed to respective ones of a plurality of programming levels and (b) a corresponding program verify phase. The control logic further identifies memory cells of the plurality of memory cells associated with a first sub-set of the plurality of programming levels to be verified during the program verify phase, the first sub-set comprising two or more dynamically selected programming levels comprising at least a lowest programming level and a second lowest programing level of the respective ones of the plurality of programming levels. The control logic further causes a first program verify voltage to be applied to the selected wordline during the program verify phase, and performs concurrent sensing operations on the identified memory cells of the plurality of memory cells associated with the first sub-set of the plurality programming levels to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the first sub-set of the plurality of programming levels during the program phase of the first loop of the program operation.

A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a judging circuit. The cell array includes plural multi-level memory cells in an m×n array. The cell array is connected with m word lines and n lines. The current supply circuit provides one of plural reference currents according to a current control value. The path selecting circuit is connected with the current supply circuit and the n bit lines. The judging circuit is connected with the path selecting circuit, and generates n output data. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first judging device of the judging circuit is connected with the first path selector and generates a first output data.

Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.

Resistive memory sensing methods and devices are described. One such method includes performing a voltage based multiple pass sensing operation on a group of cells coupled to a selected conductive line of an array of resistive memory cells. The voltage based multiple pass sensing operation can include providing an indication of those cells of the group that conduct at least a threshold amount of current responsive to one of a number of different sense voltages successively applied to the selected conductive line during each of a corresponding number of the multiple passes, and for each successive pass of the multiple passes, disabling data lines corresponding to those cells determined to have conducted the threshold amount of current in association with a previous one of the multiple passes.

A memory system in accordance with an embodiment may include a memory chip and a controller. The memory chip may store data in a plurality of logical pages by performing a sensing operation on a selected page in response to commands and performing an output operation of the data. The controller may transmit the commands to the memory chip so that a part of the sensing operation and a part of the output operation are simultaneously performed.