A method and solid-state storage device are disclosed for validating erasure status of data blocks on a solid-state drive. The method includes assigning each data block of a plurality of data blocks on the solid-state drive, a block identifier and an erasure status, the block identifier being system data, user data, or unmapped data, and the erasure status being erased or not erased.

The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of single-level-cell units and a plurality of triple-level cell units. The controller performs a first predetermined number of read processes on a second predetermined number of specific single-level-cell units to program data stored in the second predetermined number of specific single-level-cell units into a specific triple-level cell unit of the triple-level cell units and determines whether any of the second predetermined number of specific single-level-cell units has not been read successfully by any of the read processes when the specific triple-level cell unit cannot be read successfully.

According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

A memory device includes: one or more planes each including a plurality of memory blocks; and a control circuit for selectively performing a dummy read operation before a valid read operation on the first memory block, according to whether a read command on the first memory block is firstly received from a host after a program operation is performed on a plane including the first memory block.

A flash memory, a method of erasing the flash memory and an electronic system are disclosed. Each memory block in the flash memory is added with corresponding information bit(s) that store(s) information indicating whether erasure of the memory block has been completed before power-off. This allows easily finding out which memory block in the flash memory is undergoing an erase operation at the time of power-off. When the flash memory is powered on again, the information in the corresponding information bit(s) of the memory blocks may be read out and checked to determine whether there is any memory block of which the erasure had not been completed before the last power-off. If so, the memory blocks in the flash memory will be reprogrammed during the re-powering. This can avoid possible failure in reading data from some memory cells in the flash memory.

A NOR flash memory apparatus and a recover and read method for the NOR flash memory apparatus are described. The recover and read method includes: operating a power-up process on the NOR flash memory apparatus during a power-up time period; operating a power-up reading operation and reading a mark bit of a memory block of the flash memory apparatus during a reading time period after the power-up time period; and, applying a negative voltage to a plurality of un-selected word lines for the power-up reading operation to operate without leakage current from bit lines of the memory block being caused and therefore to operate normally without causing mistakes.

According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.

A data storage device including a flash memory and a controller. The flash memory has a plurality of single-level-cell units and a plurality of triple-level cell units. The controller performs a first predetermined number of read processes on a second predetermined number of specific single-level-cell units to program data stored in the second predetermined number of specific single-level-cell units into a specific triple-level cell unit of the triple-level cell units and determines whether any of the second predetermined number of specific single-level-cell units has not been read successfully by any of the read processes when the specific triple-level cell unit cannot be read successfully.

A system includes a memory device and a processing device coupled to the memory device. The memory device can include memory cells. The processing device can store operation system data in the memory cells in a single level cell (SLC) mode. The processing device can assert a flag indicating that the data written to the memory cells in the SLC mode is to remain stored in the SLC mode. The processing device can de-assert the flag, thereby indicating that the data is foldable into memory cells in a non-SLC mode.