The present disclosure includes apparatuses and methods for programming memory cells using asymmetric current pulses. An embodiment includes a memory having a plurality of self-selecting memory cells, and circuitry configured to program a self-selecting memory cell of the memory by applying a first current pulse or a second current pulse to the self-selecting memory cell, wherein the first current pulse is applied for a longer amount of time than the second current pulse and the first current pulse has a lower amplitude than the second current pulse.

Circuit and method for controlling a resistive memory formed by resistive memory cells each provided with a resistive memory element associated in series with a selector, each cell implementing a coding referred to as “multi-level” coding and being programmed in a given programming state among k (with k>2) possible programming states, wherein during a read operation, a sequence of different read voltages are applied to the given cell, and at each applied read voltage it is detected whether the read current passing through said given cell consecutively to the application of said read voltage corresponds to a leakage current level of the selector when this selector is in an off state or to a current level when the selector is in an on state.

A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H.sub.2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.

A control method to operate a memory device, a control method to operate a memory system and a control system are provided. The control method includes providing a first voltage to a memory device for accessing a memory element of the memory device; obtaining an aging information of the memory device; and providing a second voltage to the memory device according to the aging information, wherein the first voltage and the second voltage are reverse biased voltages.

The generation of “fingerprints”, also called challenge-response pairs (CRPs) of Physically Unclonable Functions (PUFs), can often stress electronic components, leaving behind traces that can be exploited by crypto-analysts. A non-intrusive method to generate CRPs based on Resistive RAMs may instead be used, which does not disturb the memory cells. The injection of small electric currents (magnitude of nanoAmperes) in each cell causes the resistance of each cell to drop abruptly by several orders of magnitudes through the formation of temporary conductive paths in each cell. A repeated injection of currents into the same cell, results in an almost identical effect in resistance drop for a single cell. However, due to the small physical variations which occur during manufacturing, the cells are significantly different from each other, in such a way that a group of cells can be used as a basis for PUF authentication.

This invention relates to memtransistors, fabricating methods and applications of the same. The memtransistor includes a polycrystalline monolayer film of an atomically thin material. The polycrystalline monolayer film is grown directly on a sapphire substrate and transferred onto an SiO.sub.2/Si substrate; and a gate electrode defined on the SiO.sub.2/Si substrate; and source and drain electrodes spatially-apart formed on the polycrystalline monolayer film to define a channel region in the polycrystalline monolayer film therebetween. The gate electrode is capacitively coupled with the channel region.

A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

Provided herein may be a resistive memory device and a method of operating the resistive memory device. The resistive memory device may include strings coupled between one or more source lines and one or more bit lines, each string including a set of one or more resistive memory cells, one or more word lines respectively coupled to the set of one or more resistive memory cells; and a voltage generator configured to control a level of a turn-on voltage to be applied to one or more unselected word lines among the one or more word lines depending on a program target state of a subset of resistive memory cells including one or more resistive memory cells selected from among the set of one or more resistive memory cells.

According to one embodiment, a memory device includes a first wiring line, a second wiring line, a memory cell connected between the first and second wiring lines, including a resistance change memory element having first and second resistance states, and a two-terminal switching element connected in series to the resistance change memory element, and a voltage application circuit which applies a write voltage signal having a first polarity and setting a desired resistance state to the resistance change memory element, to the memory cell, and applies, after the write voltage signal is applied to the memory cell, a second polarity voltage signal having a magnitude that prevents the two-terminal switching element from being set to the on-state, to the memory cell.

A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.