A resistive random access memory array and an operation method therefor, and a resistive random access memory circuit. The resistive random access memory array includes multiple memory cells, multiple bit lines, multiple word lines, multiple block selection circuits, and multiple initialization circuits. Each memory cell includes a resistive random access memory device and a switching device. The multiple memory cells are arranged into multiple memory cell rows and multiple memory cell columns in a first direction and a second direction, and the multiple bit lines and the multiple memory cell columns are connected in one-to-one correspondence. Each block selection circuit is configured to write a read/write operation voltage into a correspondingly connected bit line in response to a block selection voltage. Each initialization circuit is configured to write an initialization operation voltage to a correspondingly connected bit line in response to an initialization control voltage.

A phase change (PCM) memory device that includes a PCM and a resistance-capacitance (RC) circuit. The PCM has one or more PCM properties, each PCM property has a plurality of PCM property states. As the PCM property states of a given property are Set or Reset, the PCM property states each produce an incremental change to a property level of the respective/associated PCM property, e.g., PCM conductance. The incremental changes to property level of the PCM memory device are in response to application of one or more of a pulse number of voltage pulses. The RC circuit produces a configuring current that flows through the PCM in response to one or more of the voltage pulses. The configuring current modifies one or more of the incremental changes to one or more of the property levels so that the property level changes lineally with respect to the pulse number. The PCM memory device has use in a synapse connector, e.g., in a memory array. The memory array can be used to store and/or read memory values associated with one or more of the property levels. The memory values can be used as weighting values in a neuromorphic computing application/system, like a neural network.

A memory device includes a memory cell and a controller. The memory cell includes: (a) an array of molecule chains, at least one molecule chain includes: (i) first and second binding sites positioned at first and second ends of the molecule chain, respectively, and (ii) a chain of one or more fullerene derivatives, chemically connecting between the first and second binding sites, (b) source and drain electrodes, electrically connected to the first and second binding sites, respectively, and configured to apply to the array a source-drain voltage (VSD) along a first axis, and (c) a gate electrode, configured to apply to the array a gate voltage (VG) along a second different axis. The controller is configured to perform a data storage operation in the memory cell by (i) applying to the gate electrode a signal for producing the VG, and (ii) applying the VSD between the source and drain electrodes.

A resistive random access memory includes a memory cell including a resistive element having a resistance which varies according to a write operation and stores data according to the resistance of the resistive element, a reference resistive element having a resistance set to a first value, a voltage line set to a first voltage during a first write operation in which the resistance of the resistive element is varied from a second value higher than the first value to the first value, and a voltage control circuit arranged between first ends of the two resistive elements. The voltage control circuit adjusts a value of the first voltage supplied from the voltage line so as to reduce a difference between currents flowing through the two resistive elements during the first write operation, and supply the adjusted first voltage to the first ends of the two resistive elements.

Embodiments provide a selector device for selecting a memory cell. The selector device includes a first electrode; a second electrode; and a switching layer sandwiched between the first electrode and the second electrode. The switching layer includes at least one metal rich layer and at least one chalcogenide rich layer. The metal rich layer includes at least one of a metal or a metal compound, wherein metal content of the metal rich layer is greater than 50 at. %. The chalcogenide content of the chalcogenide rich layer is greater than 50 at. %.

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

Disclosed are methods, systems and devices for generation of a read signal to be applied across a load for use in detecting a current impedance state of the load. In one implementation, a voltage and current of a generated read signal may be controlled so as to maintain a current impedance state of the load.

A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.

The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to count a number of program operations performed on the memory cells of the memory during operation of the memory, and increase a magnitude of a current used to sense a data state of the memory cells of the memory upon the count of the number of program operations reaching a threshold count.