A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.

A semiconductor integrated circuit device may include a first signal line, a second signal line, a variable resistance material layer, and a third signal line. The second signal line may be positioned coplanar with the first signal line. The second signal line may be parallel to the first signal line. The variable resistance material layer may include a horizontal region arranged on the first and second signal lines, and may include a vertical region extending upwardly from an end of the horizontal region. The third signal line may be positioned on a plane different from a plane on which the first and second signal lines may be positioned. The third signal line may be arranged on an end of the vertical region of the variable resistance material layer.

Resistive elements for PCM RPUs and techniques for fabrication thereof using trench depth pattering are provided. In one aspect, an RPU device includes: a first electrode; a second electrode; a heater; and a PCM disposed over the first electrode, the second electrode and the heater, wherein the heater includes a combination of a first material having a resistivity r1 and a second material having a resistivity r2, wherein r1>r2, and wherein only the first material is present beneath the PCM and forms a resistive heating element. A method of operating an RPU device is also provided.

Resistive elements for PCM RPUs and techniques for fabrication thereof using trench depth pattering are provided. In one aspect, an RPU device includes: a first electrode; a second electrode; a heater; and a PCM disposed over the first electrode, the second electrode and the heater, wherein the heater includes a combination of a first material having a resistivity r1 and a second material having a resistivity r2, wherein r1>r2, and wherein only the first material is present beneath the PCM and forms a resistive heating element. A method of operating an RPU device is also provided.

A multiply-accumulate calculation device includes: a plurality of first multiple calculation elements configured to generate first output signals by multiplying a first input signal corresponding to an input value by a weight and output the first output signals; and an accumulate calculation unit configured to calculate a sum of the first output signals output from the plurality of first multiple calculation elements in a calculation period from a point in time at which transition to a steady state has occurred after transient responses caused by charging to parasitic capacitors of the plurality of first multiple calculation elements according to input of the first input signal to a point in time after transient responses caused by discharging from the parasitic capacitors of the plurality of first multiple calculation elements according to input of the first input signal have started to be generated.

An ionic transistor including a first source, a first drain spaced apart from the first source, and a first storage layer electrically connected to the first source and the first drain. The ionic transistor also includes a second source spaced apart from the first source, a second drain spaced apart from the second source, and a second storage layer electrically connected to the second source and the second drain. The ionic transistor further includes an electrolyte layer situated between and electrically connected to the first and second storage layers. The ionic transistor may be implemented as non-volatile memory in a machine learning (ML) application.

A nonvolatile memory cell includes a semiconductor layer including a first recess and a second recess. A first gate insulation layer is disposed on a bottom surface and side surfaces of the first recess. A second gate insulation layer is disposed on a bottom surface and side surfaces of the second recess. A variable resistive material layer is disposed on a first region of the semiconductor layer disposed between the first and second recesses. An insulation barrier layer disposed on a top surface and side surfaces of the variable resistive material layer. A gate electrode surrounding the insulation barrier layer and extending to fill the first and second recesses.

A nonvolatile memory cell includes a semiconductor layer including a first recess and a second recess. A first gate insulation layer is disposed on a bottom surface and side surfaces of the first recess. A second gate insulation layer is disposed on a bottom surface and side surfaces of the second recess. A variable resistive material layer is disposed on a first region of the semiconductor layer disposed between the first and second recesses. An insulation barrier layer disposed on a top surface and side surfaces of the variable resistive material layer. A gate electrode surrounding the insulation barrier layer and extending to fill the first and second recesses.

A carbon nanotube (CNT) single ion memory (or memory device) may include a mobile ion conductor with a CNT on one side and an ion drift electrode (IDE) on the other side. The mobile ion conductor may be used as a transport medium to shuttle ions to and from the CNT and the IDE. The IDE may move the ions towards or away from the CNT.

A method for improving an integrated circuit design which has transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design circuitry which, when activated, repairs the particular transistor by self-heating. The method can comprise determining a memory cell that has a read current below a passing criteria, the memory cell having a transistor with a nanowire channel on a current path through which the read current flows; and applying a stress on the memory cell to repair the nanowire channel of the transistor in the memory cell on the current path. The determining step can include sensing read currents of memory cells in an array of memory cells; and determining one or more memory cells in the array of memory cells having read currents below the passing criteria, using the read currents sensed.