A complementary resistive switching (CRS) memory device having a three-dimensional crossbar-point vertical multi-layer structure is provided. The CRS memory device having a three-dimensional structure comprises: a conductive pillar; a plurality of CRS memory unit devices surrounding an outer circumferential surface of the conductive pillar and positioned to be spaced apart from each other; and a plurality of word electrode lines making contact with outer circumferential surfaces of the CRS memory unit devices and positioned so as to intersect the conductive pillar, wherein the CRS memory unit devices comprise: a first oxide semiconductor film surrounding the outer circumferential surface of the conductive pillar; a conductive film surrounding the first oxide semiconductor film; and a second oxide semiconductor film surrounding the conductive film. Therefore, a CRS memory device having a CRS-based three-dimensional crossbar-point vertical structure can be provided wherein a CRS device having a three-layer structure is applied as a unit device so as to enable efficient writing and reading without a selection device.

Resistive RAM (RRAM) devices having increased uniformity and related manufacturing methods are described. Greater uniformity of performance across an entire chip that includes larger numbers of RRAM cells can be achieved by uniformly creating enhanced channels in the switching layers through the use of radiation damage. The radiation, according to various described embodiments, can be in the form of ions, electromagnetic photons, neutral particles, electrons, and ultrasound.

Provide a resistive random-access memory device having an optimized 3D construction. A resistive random-access memory includes a plurality of pillars, a plurality of bit lines, and a memory cell. The pillars extend vertically along the main surface of the substrate. The bit lines extend in a horizontal direction. The memory cell is formed at the intersection of the pillars and the bit lines. The memory cell includes a gate insulating film, a semiconductor film, and a resistive element. The gate insulating film is formed on the circumference of the pillar. The semiconductor film is formed on the circumference of gate insulating film and provides a channel area. The resistive element is formed on the circumference of the semiconductor film. A first electrode area on the circumference of the resistive element and a second electrode area facing the first electrode area are electrically connected to a pair of adjacent bit lines.

A semiconductor device includes a substrate and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer and at least one interlayer insulating layer that are alternately stacked over the substrate. The semiconductor device includes a hole pattern penetrating the gate structure over the substrate, and a gate insulating layer, a channel layer, a resistor layer, and a resistance changing layer sequentially disposed on a sidewall surface of the gate structure within the hole pattern. Each of the resistor layer and the resistance changing layer is disposed opposite to the gate insulating layer, based on the channel layer.

Provided is a resistive random-access memory device, including: multiple pillars, extending in a vertical direction with respect to a main surface of a substrate; multiple bit lines, extending in a horizontal direction with respect to the main surface of the substrate; and a memory cell, formed at an intersection of the pillars and the bit lines. The memory cell includes a gate insulating film formed on an outer periphery of the pillars, a semiconductor film formed on an outer periphery of the gate insulating film and providing a channel region, and a variable resistance element formed on a part of an outer periphery of the semiconductor film. An electrode region of an outer periphery of the variable resistance element is connected to one of a pair of adjacent bit lines, and the semiconductor film is connected to the other of the pair of adjacent bit lines.

There are provided a variable resistance memory device and a manufacturing method of the same. The variable resistance memory device includes: a first electrode; a second electrode arranged in a vertical direction from the first electrode; and an oxide layer having an oxygen deficient region extending in the vertical direction between the second electrode and the first electrode.

There are provided a variable resistance memory device and a manufacturing method of the same. The variable resistance memory device includes: a first electrode; a second electrode arranged in a vertical direction from the first electrode; and an oxide layer having an oxygen deficient region extending in the vertical direction between the second electrode and the first electrode.

A quantum hybridization negative differential resistance device having negative differential resistance (NDR) under a low voltage condition using a nanowire based on an organic-inorganic hybrid halide perovskite, and a circuit thereof are provided. The quantum hybridization negative differential resistance device includes a channel formed of an organic-inorganic hybrid halide perovskite crystal and electrodes formed of its inorganic framework and is connected to opposite ends of the channel.

Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.

This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; a bitline, suspended on the substrate; a bottom electrode, wrapped around the bitline; a resistive layer, wrapped around the bottom electrode; a top electrode, wrapped around the resistive layer; and a wordline electrode, disposed around the top electrode and connected to the top electrode.