A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

A switch device includes a first electrode, a second electrode, and a switch layer. The second electrode is disposed to face the first electrode. The switch layer is provided between the first electrode and the second electrode. The switch layer contains an amorphous material made of at least germanium (Ge) and one of nitrogen (N) and oxygen (O).

Provided are memory cells, such as resistive random access memory (ReRAM) cells, each cell having multiple metal oxide layers formed from different oxides, and methods of manipulating and fabricating these cells. Two metal oxides used in the same cell have different dielectric constants, such as silicon oxide and hafnium oxide. The memory cell may include electrodes having different metals. Diffusivity of these metals into interfacing metal oxide layers may be different. Specifically, the lower-k oxide may be less prone to diffusion of the metal from the interfacing electrode than the higher-k oxide. The memory cell may be formed to different stable resistive levels and then resistively switched at these levels. Each level may use a different switching power. The switching level may be selected a user after fabrication of the cell and in, some embodiments, may be changed, for example, after switching the cell at a particular level.

A resistive memory device includes a first electrode, a memristor coupled in electrical series with the first electrode, a second electrode coupled in electrical series with the memristor, a selector coupled in electrical series with the second electrode, and a third electrode coupled in electrical series with the selector. The memristor includes oxygen or nitrogen elements. The selector includes a composite dielectric material of a first dielectric material, a second dielectric material that is different from the first dielectric material, and a dopant material including a cation having a migration rate faster than the oxygen or the nitrogen elements of the memristor. The first dielectric material and the second dielectric material are present in a ratio ranging from 1:9 to 9:1, and a concentration of the dopant material in the composite dielectric material ranges from about 1% up to 50%.

According to one embodiment, a semiconductor memory device includes a semiconductor layer, a gate electrode, a metal containing portion, and an insulating portion. The semiconductor layer includes a first region and a second region. The second region has at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region. The gate electrode is apart from the first region in a first direction. The first direction crosses a second direction connecting the first region and the second region. The metal containing portion is apart from the second region in the first direction. At least a part of the metal containing portion overlaps the gate electrode in the second direction. The insulating portion is provided between the gate electrode and the first region and between the metal containing portion and the second region.

According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to perform transition of a resistive state of the memory cell. The control circuit performs a first writing operation by applying a first pulse having a voltage of a first polarity to the memory cell and applying a second pulse having a voltage of the first polarity smaller than the voltage of the first pulse to the memory cell continuously after applying the first pulse.

A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

There are provided a variable resistance memory device and a manufacturing method of the same. The variable resistance memory device includes: a first electrode; a second electrode arranged in a vertical direction from the first electrode; and an oxide layer having an oxygen deficient region extending in the vertical direction between the second electrode and the first electrode.

Described is a memory cell which comprises: a transistor positioned in a backend of a die, the transistor comprising: a source structure and a drain structure; a gate structure between the source structure and the drain structure; a source contact coupled to and above the source structure and a drain contact coupled to and below the drain structure; and a Resistive Random Access Memory (RRAM) device coupled to the drain contact.