A memory device includes a memory cell and a controller. The memory cell includes: (a) an array of molecule chains, at least one molecule chain includes: (i) first and second binding sites positioned at first and second ends of the molecule chain, respectively, and (ii) a chain of one or more fullerene derivatives, chemically connecting between the first and second binding sites, (b) source and drain electrodes, electrically connected to the first and second binding sites, respectively, and configured to apply to the array a source-drain voltage (VSD) along a first axis, and (c) a gate electrode, configured to apply to the array a gate voltage (VG) along a second different axis. The controller is configured to perform a data storage operation in the memory cell by (i) applying to the gate electrode a signal for producing the VG, and (ii) applying the VSD between the source and drain electrodes.

Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.

This invention relates to memtransistors, fabricating methods and applications of the same. The memtransistor includes a polycrystalline monolayer film of an atomically thin material. The polycrystalline monolayer film is grown directly on a sapphire substrate and transferred onto an SiO.sub.2/Si substrate; and a gate electrode defined on the SiO.sub.2/Si substrate; and source and drain electrodes spatially-apart formed on the polycrystalline monolayer film to define a channel region in the polycrystalline monolayer film therebetween. The gate electrode is capacitively coupled with the channel region.

The present disclosure provides a memory device, which includes a plurality of electrically bipolar variable memory devices and a storage transistor. The electrically bipolar variable memory devices are electrically connected to a plurality of word lines respectively, the storage transistor is electrically connected to the electrically bipolar variable memory devices, where one end of each of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the word lines, and another end of each of the electrically bipolar variable memory devices is electrically connected to the gate of the storage transistor.

A storage device for generating an identity code and an identity code generating method are disclosed. The storage device includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores a plurality of first data and the first data have a plurality of bits. The second storage circuit stores a plurality of second data and the second data have a plurality of bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, selects a first portion of the first data according to the first sequence, reads the first portion of the first data from the first storage circuit to form a target sequence and outputs the target sequence to serve as an identity code.

An embodiment in the application may include an analog memory structure, and methods of writing to such a structure, including a volatile memory element in series with a non-volatile memory element. The analog memory structure may change resistance upon application of a voltage. This may enable accelerated writing of the analog memory structure.

Crossbar arrays perform analog vector-matrix multiplication naturally and provide a building block for modern computing systems. In many applications, the weights stored in the crossbar array are learned off-line and then stored on embedded devices. After the weights are learned, they do not change. Since the weights do not change in these applications, this disclosure envisions a new implementation for the processing elements of the crossbar array.

A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.

A memory including a memory array having a plurality of bit-line inputs and a plurality of word-line inputs; a bit-line decoder; and a control circuit is provided. The bit-line decoder includes a first circuit and a second circuit including a plurality of low-voltage field effect transistors (FET). The control circuit provides control signals to the plurality of low-voltage FETs in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein at the pulse phase, the first circuit and the second circuit receives a desired voltage. The control circuit provide control signals the plurality of low-voltage FETs a voltage no greater than a low-voltage at the pre-pulse phase and the post-pulse phase. In silicon-on-insulator (SOI) technologies, use of low-voltage FETs in the bit-line and word-line decoders reduces the area of the periphery circuits of the memory array without requiring change to the memory array itself.

Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.