Patent classifications
G11C2213/54
High electron affinity dielectric layer to improve cycling
Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.
Increasing selector surface area in crossbar array circuits
Technologies relating to increasing the surface area of selectors in crossbar array circuits are provided. An example apparatus includes: a substrate; a first line electrode formed on the substrate; an RRAM stack formed on the first line electrode, wherein the RRAM stack; an isolation layer formed beside the RRAM stack, wherein the isolation layer includes an upper surface and a sidewall, and a height from the upper surface to the first line electrode is 100 nanometers to 10 micrometers; a selector stack formed on the RRAM stack, the sidewall, and the upper surface; and a second line electrode formed on the selector stack.
HIGH ELECTRON AFFINITY DIELECTRIC LAYER TO IMPROVE CYCLING
Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.
FERROELECTRIC TUNNEL JUNCTION DEVICES WITH INTERNAL BIASES FOR LONG RETENTION
A ferroelectric tunnel junction (FTJ) memory device may include a first electrode and a ferroelectric layer comprising ferroelectric dipoles that may generate a first electric field. The first electric field may be oriented in a first direction when the device operates in an ON state. The device may also include a barrier layer that may generate a depolarizing second electric field that may be oriented in a second direction opposite of the first direction when the device operates in the ON state. The device may further include a second electrode. The first electrode and the second electrode may generate a third electric field that is oriented in the first direction when the device operates in the ON state.
Ferroelectric components and cross point array devices including the ferroelectric components
A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.
FERROELECTRIC COMPONENTS AND CROSS POINT ARRAY DEVICES INCLUDING THE FERROELECTRIC COMPONENTS
A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.
Threshold switch structure and memory cell arrangement
Various aspects relate to a threshold switch structure and a use of such threshold switch structure as a threshold switch in a memory cell arrangement, the threshold switch structure including: a first electrode, a second electrode, a switch element in direct physical contact with the first electrode and the second electrode, the switch element including a layer of a spontaneously polarizable material. The first electrode, the second electrode, and the switch element are configured to allow for a switching of the switch element between a first electrical conductance state and a second electrical conductance state as a function of a voltage drop provided over the switch element by the first electrode and the second electrode.
INCREASING SELECTOR SURFACE AREA IN CROSSBAR ARRAY CIRCUITS
The present application provides an apparatus, including: a substrate; a first line electrode formed on the substrate; an interlayer formed on the first line electrode, a selector stack formed on the interlayer and the first line electrode; an RRAM stack formed on the selector stack; and a second line electrode formed on the RRAM stack. The interlayer comprises an upper surface and a sidewall. In some embodiments, a shape of the interlayer comprises a cylinder, a pyramid, a prism, a cone, a pillar, or a protrusion;
Magnetic tunnel junction memory devices including crystallized boron-including first magnetic layer on a tunnel barrier layer and lower boron-content second magnetic layer on the first magnetic layer
Magnetic memory devices include a magnetic tunnel junction including a free layer, a pinned layer, and a tunnel barrier layer between the free layer and the pinned layer. At least one of the free layer and the pinned layer includes a first vertical magnetic layer on the tunnel barrier layer and including boron (B), and a second vertical magnetic layer on the first vertical magnetic layer and having a lower B content than the first vertical magnetic layer. The first vertical magnetic layer is between the tunnel barrier layer and the second vertical magnetic layer, and a thickness of the second vertical magnetic layer is thinner than a thickness of the first vertical magnetic layer.
Two-terminal reversibly switchable memory device
A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.