An information processing device, including a resistive analog neuromorphic device element having a pair of electrodes and an oxide layer provided between the pair of electrodes, and a parallel circuit having a low resistance component and a capacitance component. The parallel circuit and the resistive analog neuromorphic device element are connected in series.

A method for forming a nonvolatile PCM logic device may include providing a PCM film component having a first end contact distally opposed from a second end contact, positing a first proximity adjacent to a first surface of the PCM film component, positing a second proximity heater adjacent to a second surface of the PCM film component, wherein the first proximity heater and the second proximity heater are electrically isolated from the PCM film component. The method may further include applying a combination of pulses to one or more of the first proximity heater and the second proximity heater to change a resistance value of the PCM film component corresponding to a logic truth table. Further, the method may include simultaneously applying a first combination of reset pulses to program, or set pulses to initialize, the PCM film component, to the first proximity heater and the second proximity heater.

A memory device includes at least one memory cell which contains a resistive memory element having a conductive metal oxide located between a first electrode and a second electrode. The conductive metal oxide has a concentration of free electrons in thermodynamic equilibrium in a range from 1.0×10.sup.20/cm.sup.3 to 1.0×10.sup.21/cm.sup.3. A method of operating the memory device includes redistributing electron density to set and reset the device. An oxide barrier layer may be located between the conductive metal oxide and the second electrode.

Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode.

A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least one interfacial layer includes an oxygen reservoir that can store oxygen atoms during operation of the resistive memory element. The at least one interfacial layer can include an interfacial metal oxide layer, a metal layer, and optionally, a ruthenium layer.

Disclosed is a solid state memory having a non-linear current-voltage (I-V) response. By way of example, the solid state memory can be used as a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the nonvolatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

The techniques described herein relate to methods and apparatus for a resistive switching device. The resistive switching device includes a first electrode formed in a substrate. The resistive switching device also includes a plurality of layers formed above the first electrode, including a plurality of oxide layers, wherein one or more of the plurality of oxide layers comprise doped oxide layers, and one or more conductive spacers, wherein each pair of oxide layers of the plurality of oxide layers are separated by a conductive spacer of the one or more conductive spacers. The resistive switching device also includes a second electrode formed above the plurality of layers, such that the first electrode, the plurality of layers, and the second electrode are in series.

Disclosed is a solid state memory having a non-linear current-voltage (I-V) response. By way of example, the solid state memory can be used as a selector device. The selector device can be formed in series with a nonvolatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the nonvolatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

A method for manufacturing a semiconductor device includes forming a memory element in a dielectric layer. A first conductive layer is deposited on the dielectric layer and the memory element by atomic layer deposition, and a second conductive layer is deposited on the first conductive layer by physical vapor deposition. In the method, the first and second conductive layers are patterned into an electrode on the memory element.

Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.