Examples for ultra-precise tuning of a selected memory cell are disclosed. In one example, a method of programming a first memory cell in a neural memory to a target value is disclosed, the method comprising programming a second memory cell by applying programming voltages to terminals of the second memory cell; and determining if an output of the first memory cell has reached the target value.

Embodiments for ultra-precise tuning of a selected memory cell are disclosed. The selected memory cell optionally is first programmed using coarse programming and fine programming methods. The selected memory cell then undergoes ultra-precise programming through the programming of an adjacent memory cell. As the adjacent memory cell is programmed, capacitive coupling between the floating gate of the adjacent memory cell and the floating gate of the selected memory cell will cause the voltage of the floating gate of the selected memory cell to increase, but in smaller increments than could be achieved by programming the selected memory cell directly. In this manner, the selected memory cell can be programmed with ultra-precise gradations.

Embodiments for ultra-precise tuning of a selected memory cell are disclosed. The selected memory cell optionally is first programmed using coarse programming and fine programming methods. The selected memory cell then undergoes ultra-precise programming through the programming of an adjacent memory cell. As the adjacent memory cell is programmed, capacitive coupling between the floating gate of the adjacent memory cell and the floating gate of the selected memory cell will cause the voltage of the floating gate of the selected memory cell to increase, but in smaller increments than could be achieved by programming the selected memory cell directly. In this manner, the selected memory cell can be programmed with ultra-precise gradations.

Quantum dot circuit and a method of characterizing such a circuit Voltages that enable control of electron occupation in a series of quantum dots are determined by a method of measuring effects of gate electrode voltages on a quantum dot circuit. The quantum dot circuit comprises a channel (10), first gate electrodes (14a-14e) that extend over locations along the edge of the channel to create potentials barriers defining the potentials well therebetween, as well as second gate electrodes (16a-16d) adjacent to potential wells, for controlling depths of the successive electrical potential wells between the potential barriers. First, channel currents are measured in a pre-scan of bias voltages of the first gates for controlling the potential barriers. The result is used to set their bias levels in, a scan over a two-dimensional range of combinations of bias voltages on the second gates for controlling the depths. In this scan an indication of charge carrier occupation of potential wells at consecutive positions along the channel such as electromagnetic wave reflection is measured. Pattern matching with a pattern of crossing occupation edges is applied to the result. This involves a two-dimensional image that has the combinations of the bias voltages as image points and the indication of charge carrier occupation as image values. The pattern matching detects an image point where the image matches a pattern of crossing edges along predetermined directions.

Quantum dot circuit and a method of characterizing such a circuit Voltages that enable control of electron occupation in a series of quantum dots are determined by a method of measuring effects of gate electrode voltages on a quantum dot circuit. The quantum dot circuit comprises a channel (10), first gate electrodes (14a-14e) that extend over locations along the edge of the channel to create potentials barriers defining the potentials well therebetween, as well as second gate electrodes (16a-16d) adjacent to potential wells, for controlling depths of the successive electrical potential wells between the potential barriers. First, channel currents are measured in a pre-scan of bias voltages of the first gates for controlling the potential barriers. The result is used to set their bias levels in, a scan over a two-dimensional range of combinations of bias voltages on the second gates for controlling the depths. In this scan an indication of charge carrier occupation of potential wells at consecutive positions along the channel such as electromagnetic wave reflection is measured. Pattern matching with a pattern of crossing occupation edges is applied to the result. This involves a two-dimensional image that has the combinations of the bias voltages as image points and the indication of charge carrier occupation as image values. The pattern matching detects an image point where the image matches a pattern of crossing edges along predetermined directions.

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

The present disclosure relates to novel memristive devices, uses thereof, and processes for their preparation. In a first aspect, the disclosure provides a quantum memristor, including a first quantum dot (QD1) which is capacitively coupled to a second quantum dot (QD2), a source electrode, a drain electrode, and a bath electrode, wherein the source electrode and the drain electrode are coupled via quantum tunneling to QD1 and the bath electrode is coupled via quantum tunneling to QD2, and wherein QD2 is capacitively coupled to either the source electrode or the drain electrode.

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

The present disclosure relates to novel memristive devices, uses thereof, and processes for their preparation. In a first aspect, the disclosure provides a quantum memristor, including a first quantum dot (QD1) which is capacitively coupled to a second quantum dot (QD2), a source electrode, a drain electrode, and a bath electrode, wherein the source electrode and the drain electrode are coupled via quantum tunnelling to QD1 and the bath electrode is coupled via quantum tunnelling to QD2, and wherein QD2 is capacitively coupled to either the source electrode or the drain electrode.

According to one embodiment, a quantum annealing machine 1 includes a quantum bit array 21 which includes a plurality of cells (quantum bits) 211 respectively including a floating gate 105, and a controller 10 which executes writing of data in the plurality of cells 211, and temporally controls tunneling of an electric charge with respect to the floating gate 105.