Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.

A signal processing method includes the following operations: receiving an input signal and analyzing the input signal to generate a plurality of bit codes by a signal receiving circuit; temporarily storing a first part of the plurality of bit codes according to a time sequence by a shift register and starting a decoder when the shift register is full; and performing a boundary calibration according to the first part of the plurality of bit codes by the decoder when the first part of the plurality of bit codes meets a decoding table rule and a boundary detection rule.

A memory device can sense stored data during memory read operations using a reference trim, and a memory built-in self-test system can perform a multiple step process to set the reference trim for the memory device. The memory built-in self-test system can set a reference trim range that corresponds to a range of available reference trim values and then select one of the reference trim values in the reference trim range as the reference trim for the memory device. The memory built-in self-test system can set the reference trim range by prompting performance of the memory read operations using different positions of the reference trim range relative to read characteristics of the memory device and set a position for the reference trim range relative to the read characteristics of the memory device based on failures of the memory device to correctly sense the stored data during the memory read operations.

A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.

A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.

A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.

A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.

A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating condition.