A memory includes a bank, the bank includes a plurality of sections, each of the plurality of section includes a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, and each of the plurality of storage units is connected to one of the plurality of word lines and one of the plurality of bit lines; the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines.

A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller includes an error correction code (ECC) circuit. The ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes. The memory controller is configured to write second data based on the buffer to the memory device.

A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller includes an error correction code (ECC) circuit. The ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes. The memory controller is configured to write second data based on the buffer to the memory device.

Methods and systems for selectively compressing data lines of a memory device in selective compression circuitry. The selective compression circuitry receives multiple data lines and compression circuitry that selectively compresses inputs. The selective compression circuitry also includes control circuitry to receive data over via the data lines. The control circuitry, when in a compressed mode, transmits data from each of the data lines to the compression circuitry. Alternatively, in an uncompressed mode, the control circuitry transmits data from a first subset of the data lines to the compression circuitry while blocking data from a second subset of the data lines from being transmitted to the compression circuitry.

A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.

The present technology may include a first storage circuit connected to a plurality of memory banks, an error correction circuit, a read path including a plurality of sub-read paths connected between the plurality of memory banks and the error correction circuit, and a control circuit configured to control data output from the plurality of memory banks to be simultaneously stored in the first storage circuit by deactivating the read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially transmitted to the error correction circuit by sequentially activating the plurality of sub-read paths during a second sub-test section.

A method for the secured storing of a data element of a predefined data type to be stored by a computer program in an external memory, which is connected to a microcontroller, an error correction value of one error correction value data type being used. The method includes, when creating the computer program: defining a composite data element that includes one element of the data type and one element of the error correction value data type, in the computer program; and when executing the computer program: calculating the error correction value for the data element to be stored; forming an error correction data element as the composite data element, which contains the data element to be stored and the associated error correction value, which has been calculated for the data element; and writing the error correction data element to a memory address for the error correction data element.

A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.

A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.

Methods, systems, and devices for data compression for global column repair are described. In some cases, a testing device may perform a first internal read operation to identify errors associated with on one or more column planes. A value (e.g., a bit) indicating whether an error occurred when testing each column plane may be stored. The testing device may perform a second internal read operation on the same column planes, or on column planes of a different bank of memory cells. The values (e.g., bits) indicating whether errors occurred during the first internal read operation and the values indicating whether errors occurred during the second internal read operation may be combined and stored in a register. The stored values may be read out (e.g., as a burst) to repair the defective column planes.