A memory device includes a system block for storing test information and includes a data block including memory cells connected to a plurality of low bank column lines and a plurality of high bank column lines. The memory device also includes a column repair controller configured to detect, based on the test information, a concurrent repair column line in which a low bank column line among the plurality of low bank column lines and a high bank column line the plurality of high bank column lines corresponding to the same column address are concurrent repaired.

A method of testing a semiconductor package including a plurality of semiconductor chips includes sensing electrical signals respectively output from a plurality of semiconductor chip groups each representing a combination of at least two semiconductor chips among the plurality of semiconductor chips, obtaining amplitudes of electrical signals respectively output from the plurality of semiconductor chips based on the plurality of sensed electrical signals, and outputting a test result for the semiconductor package by using the plurality of obtained electrical signals.

A test circuit includes a comparator and a comparison control circuit. The comparator is configured to compare a first input signal with a second input signal to generate a comparison result signal. The comparison control circuit is configured to perform at least one of an operation for latching the comparison result signal as reference data and an operation for outputting the comparison result signal as a first output signal. The comparison control circuit is configured to provide expectation data as the first input signal and read data as the second input signal in accordance with the reference data.

A method and a device for memory testing, and a computer-readable storage medium are provided. In the method, an instruction signal is sent to the memory, the instruction signal comprising a randomly generated write instruction or read instruction; a valid Column Address Strobe (CAS) instruction for ensuring running of the instruction signal is randomly inserted before the instruction signal by detecting a specific type of the instruction signal, and at least one of a redundant CAS instruction or invalid command irrelevant to the instruction signal is randomly generated and inserted; and the memory is enabled to run the instruction signal, the inserted valid CAS instruction, and the at least one of the redundant CAS instruction or the invalid command, and the running of the memory is tested.

Methods, systems, and devices for shared error correction coding (ECC) circuitry are described. For example, a memory device configured with shared ECC circuitry may be configured to receive data at the shared circuitry from either a host device or a set of memory cells of the memory device. The shared circuitry may be configured to generate a set of multiple syndromes associated with a cyclic error correction code, based on the received data. As part of an encoding process, an encoder circuit may generate a set of parity bits based on the generated syndromes. As part of a decoding process, a decoder circuit may generate an error vector for decoding the received data, based on the generated syndromes. The decoder circuit may also correct one or more errors in the received data based on generating the error vector.

A method and a testing apparatus related to wafer testing are provided. In the method, testing raw data is obtained by a testing apparatus operating with a Unix-related system. The testing raw data is a testing result of probe testing on one or more wafers by the testing apparatus. The testing raw data is converted into converted data by the testing apparatus. The converted data is related to the defect information of the wafer. Analyzed data is generated by the testing apparatus according to the converted data. The analyzed data is used for a graphical interface. Therefore, real-time defect analysis during the testing procedure may be provided.

A method of testing a non-volatile memory (NVM) array includes obtaining a current distribution of a subset of NVM cells of the NVM array, the current distribution including first and second portions corresponding to respective logically high and low states of the subset of NVM cells, programming an entirety of the NVM cells of the NVM array to one of the logically high or low states, determining an initial bit error rate (BER) by performing first and second pass/fail (P/F) tests on each NVM cell of the NVM array, and using the current distribution to adjust the initial BER rate. Each of obtaining the current distribution, programming the entirety of the NVM cells, and performing the first and second P/F tests is performed while the NVM array is heated to a target temperature.

The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.

A testing device comprises test interface circuitry, probe circuitry, and initiate state machine circuitry. The test interface circuitry is configured to receive NAND signaling when operatively coupled to a M-NAND memory device under test and to operate the M-NAND memory device under test to receive memory access requests and to provide status or data at the same rate it receives memory access requests. The probe circuitry is configured to detect memory operations of the memory device under test. The finite state machine circuitry is operatively coupled to the probe circuitry and is configured to advance through multiple circuit states according to the detected memory operations; and log memory events of the memory device under test according to the circuit states.

The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (V.sub.dd) to the gate electrode to turn on the first transistor, determining a first threshold voltage (V.sub.th) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (V.sub.ss); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.