According to an embodiment, when a storage status of a first storage unit is recognized as a protected state, a control unit writes data to a second storage unit. When a read target address is recorded in a data migration log area, the control unit reads data from the second storage unit. When the read target address is not recorded in the data migration log area, the control unit reads data from the first storage unit.

Memories, and their operation, might include a plurality of content addressable memory (CAM) cells each for storing a respective data value, a match signal generator configured to generate an indication whether each CAM cell of the plurality of CAM cells indicates a match between its respective data value and a respective received signal value, and a plurality of storage elements each for storing a respective data value, wherein each storage element of the plurality of storage elements corresponds to a respective CAM cell of the plurality of CAM cells in a one-to-one relationship, and wherein each storage element of the plurality of storage elements is responsive to the indication of the match signal generator to generate a data signal indicative of the respective data value of that storage element if a match of their corresponding CAM cells is indicated.

A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.

A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.

According to one embodiment, a storage system includes a controller. The controller receives, from a host, a write command including a block address indicating a first block in a plurality of blocks, and a page address indicating a first page of the first block. The controller writes data designated by the write command to the first page of the first block. The controller notifies the host 2 of a page address indicating a latest readable page which is included in pages of the first block, the pages containing data which was written by the host before the designated data was written to the first page, the latest readable page having become readable by writing the designated data to the first page.

According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.