A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

A radiation detection system may include a mobile device having a flash memory. The device may monitor various characteristics of the flash memory to determine when damage to the flash memory has occurred from radiation exposure. The device may associate damage to the flash memory with a radiation dose, and determine a level of radiation to which the memory, and thus the device, has been exposed. The device also may determine a length of time and locations where the radiation exposure has occurred. If the device determines that the level of radiation exposure exceeds a threshold associated with a safe level of radiation exposure for a human user, the device may generate an alert to the user.

A memory may include multiple rows each coupled to multiple memory cells; a target row classification circuit suitable for classifying, as a target row, a row, among the multiple rows, that is susceptible to data loss as a result of activity of an adjacent row; and a target row signal generation circuit suitable for sequentially activating a target row active signal for activating the target row and a target row precharge signal for precharging the target row in response to a precharge command.

Some embodiments include an integrated assembly having digit lines supported by a base and extending along a first direction. A shield-connection-line is supported by the base and extends along the first direction. Transistor active regions are over the digit lines. Each of the active regions includes a channel region between an upper source/drain region and a lower source/drain region. The lower source/drain regions are coupled with the digit lines. Capacitors are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines extend along the second direction. The shield lines are above the digit lines and are coupled with the shield-connection-line.

Methods, apparatuses, and systems related to operations for memory process feedback. A controller can monitor memory activities, such as processes, identify row hammer aggressors, and perform mitigating steps to the row hammer aggressors. The controller may have a table of addresses of row hammer aggressors and perform operations of tracking row hammer aggressors. The controller can determine whether the number of aggressors reaches a threshold. When the number of aggressors reaches the threshold, the controller can send a message with the aggressor addresses to the operating system. The operating system can perform mitigating steps to the row hammer aggressors. In some embodiments, the controller may identify the row hammer aggressors and inject poisoned data into the process to mitigate the row hammer aggressors.

A memory may include multiple rows each coupled to multiple memory cells; a target row classification circuit suitable for classifying, as a target row, a row, among the multiple rows, that is susceptible to data loss as a result of activity of an adjacent row; and a target row signal generation circuit suitable for sequentially activating a target row active signal for activating the target row and a target row precharge signal for precharging the target row in response to a precharge command.

Upon detecting power loss during the process of programming multi-level cell (MLC) memory in a storage system, the storage system takes steps to prevent data loss. In one example, the controller sends a graceful shutdown command to the memory, in response to which the memory aborts the ongoing programming operation and stores data from data latches associated with unprogrammed memory cells in single-level cell (SLC) memory. The memory can also store data from programmed memory cells in the SLC memory. The data to be programmed in the MLC memory can be reconstructed prior to powering down the storage system or after the storage system is powered back up. The reconstructed data can then be programmed in the MLC memory.

A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.

A load control device may include a semiconductor switch, a control circuit, and first and second terminals adapted to be coupled to a remote device. The load control device may include a first switching circuit coupled to the second terminal, and a second switching circuit coupled between the first terminal and the second terminal. The control circuit may be configured to render the first switching circuit conductive to conduct a charging current from an AC power source to a power supply of the remote device during a first time period of a half-cycle of the AC power source, and further configured to render the first and second switching circuits conductive and non-conductive to communicate with the remote device via the second terminal during a second time period of the half-cycle of the AC power source.

The present invention discloses a first preferred processor comprising a fixed look-up table circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the writable LTC realizes at least a non-common function. The present invention further discloses a second preferred processor comprising a two-dimensional (2-D) LTC and a three-dimensional (3-D) LTC. The 2-D LTC realizes at least a fast function while the 3-D LTC realizes at least a non-fast function.