Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.

Embodiments of the present application relate to the field of semiconductors, and provide an amplifier and a memory. The amplifier includes at least a sense amplifier, where the sense amplifier includes a pull-up driving circuit and an amplifier circuit; the pull-up driving circuit includes one terminal connected to a power supply voltage, and the other terminal connected to a power supply terminal of the amplifier circuit; the sense amplifier includes a first sense amplifier and a second sense amplifier; the first sense amplifier includes a first pull-up driving circuit and a first amplifier circuit; the second sense amplifier includes a second pull-up driving circuit and a second amplifier circuit; and both the first pull-up driving circuit and the second pull-up driving circuit are located between the first amplifier circuit and the second amplifier circuit. The embodiments of the present application are helpful to improve the layout design of the amplifier.

A semiconductor package includes a semiconductor package includes first, second, third and fourth semiconductor chips sequentially stacked on one another. Each of the first, second, third and fourth semiconductor chips includes a first group of bonding pads and a second group of bonding pads alternately arranged in a first direction and input/output (I/O) circuitry selectively connected to the first group of bonding pads respectively. Each of the first, second and third semiconductor chips includes a first group of through electrodes electrically connected to the first group of bonding pads and a second group of through electrodes electrically connected to the second group of bonding pads.

A reconfigurable compute fabric of a system can include multiple nodes, and each node can include multiple, communicatively coupled tiles with respective processing and storage elements. In an example, a tile-based processor can be configured to perform operations comprising receiving a first stencil that defines input data for a first operation. The stencil can have a height corresponding to N rows in a main memory and a stencil width corresponding to M columns in the main memory. The processor can perform operations comprising establishing N buffers in a tile memory, each buffer having M buffer elements, and populating the M buffer elements of the N buffers using respective information, defined by the first stencil, from the main memory. Tile-based stencil operations can use information from the N buffers and provide compute results in an output array.

A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.

A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. An reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

Field-effect transistors, and integrated circuit devices containing such field-effect transistors, might include a semiconductor material having a first conductivity type, a first source/drain region having a second conductivity type, a second source/drain region having the second conductivity type, a first contact connected to the first source/drain region, a conductor overlying an active area of the semiconductor material and having an annular portion surrounding the first contact and a spur portion extending from an outer perimeter of the annular portion of the conductor, a second contact connected to the second source/drain region outside the annular portion of the conductor, a dielectric between the conductor and the active area, and a third contact overlying the active area and connected to the spur portion of the conductor.

A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

A sub-sense amplifier includes a semiconductor substrate, a first pair of complementary transistors, a second pair of complementary transistors, and at least one ground transistor. The first pair and second pair of complementary transistors and the ground transistor are formed on the semiconductor substrate. The first pair of complementary transistors are disposed in line symmetry with a center line of the sub-sense amplifier as a symmetry axis, and gates of the first pair of complementary transistors are coupled to a node. The second pair of complementary transistors are also disposed in line symmetry with the center line, wherein the current directions of the second pair of complementary transistors are the same. Sources and drains of the first pair of complementary transistors are coupled to gates and sources of the second pair of complementary transistors, respectively. The ground transistor connects in series with the second pair of complementary transistors.